srenblad/artiq
1
0
Fork 0
forked from M-Labs/artiq
Code Pull Requests Activity

sawg: explain DUC

Browse Source
This commit is contained in:
Robert Jördens 2017-05-23 10:28:23 +02:00
parent bfc224d4ba
commit 52625d57f0
1 changed files with 10 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
artiq/coredevice/sawg.py
View File

@ -91,7 +91,8 @@ class Config:
@kernel
def set_duc_i_max(self, limit: TInt32):
"""Set the DUC I data summing junction upper limit.
"""Set the digital up-converter (DUC) I data summing junction upper
limit.
Each of the three summing junctions has a saturating adder with
configurable upper and lower limits. The three summing junctions are:
@ -169,6 +170,14 @@ class SAWG:
i_enable*Re(oscillators) +
q_enable*Im(buddy_oscillators))
This parametrization can be viewed as two complex (quadrature) oscillators
(``frequency1``/``phase1`` and ``frequency2``/``phase2``) followed by
a complex digital up-converter (DUC, ``frequency0``/``phase0``) on top of a
(real/in-phase) ``offset``. The ``i_enable``/``q_enable`` switches
enable emission of quadrature signals for later analog quadrature mixing
distinguishing upper and lower sidebands and thus doubling the bandwidth.
They can also be used to emit four-tone signals.
The configuration channel and the nine spline interpolators are accessible
as attributes: