forked from M-Labs/artiq
phaser: adjust to new jesd
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679060af1d
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bfc224d4ba
@ -104,10 +104,11 @@ class AD9154JESD(Module, AutoCSR):
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for i in range(4):
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phy = JESD204BPhyTX(
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qpll, platform.request("ad9154_jesd", i), fabric_freq)
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phy.gtx.cd_tx.clk.attr.add("keep")
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platform.add_period_constraint(phy.gtx.cd_tx.clk, 40*1e9/linerate)
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phy.transmitter.cd_tx.clk.attr.add("keep")
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platform.add_period_constraint(phy.transmitter.cd_tx.clk,
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40*1e9/linerate)
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platform.add_false_path_constraints(self.cd_jesd.clk,
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phy.gtx.cd_tx.clk)
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phy.transmitter.cd_tx.clk)
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self.phys.append(phy)
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to_jesd = ClockDomainsRenamer("jesd")
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self.submodules.core = to_jesd(JESD204BCoreTX(self.phys, settings,
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@ -245,7 +246,7 @@ class Phaser(MiniSoC, AMPSoC):
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self.crg.cd_sys.clk, self.ad9154.jesd.cd_jesd.clk)
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for phy in self.ad9154.jesd.phys:
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platform.add_false_path_constraints(
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self.crg.cd_sys.clk, phy.gtx.cd_tx.clk)
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self.crg.cd_sys.clk, phy.transmitter.cd_tx.clk)
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def main():
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