forked from M-Labs/artiq
drtio: add echo and packet count test
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df7294792c
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5019b03f10
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@ -55,7 +55,9 @@ class DUT(Module):
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class TestFullStack(unittest.TestCase):
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class TestFullStack(unittest.TestCase):
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def test_full_stack(self):
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clocks = {"sys": 8, "rtio": 5, "rtio_rx": 5, "rio": 5, "rio_phy": 5}
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def test_controller(self):
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dut = DUT(2)
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dut = DUT(2)
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kcsrs = dut.master.rt_controller.kcsrs
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kcsrs = dut.master.rt_controller.kcsrs
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csrs = dut.master.rt_controller.csrs
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csrs = dut.master.rt_controller.csrs
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@ -203,6 +205,31 @@ class TestFullStack(unittest.TestCase):
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cycle += 1
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cycle += 1
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run_simulation(dut,
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run_simulation(dut,
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{"sys": test(), "rtio": check_ttls()},
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{"sys": test(), "rtio": check_ttls()}, self.clocks)
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{"sys": 8, "rtio": 5, "rtio_rx": 5, "rio": 5, "rio_phy": 5})
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self.assertEqual(ttl_changes, correct_ttl_changes)
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self.assertEqual(ttl_changes, correct_ttl_changes)
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def test_echo(self):
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dut = DUT(2)
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csrs = dut.master.rt_controller.csrs
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mgr = dut.master.rt_manager
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def test():
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while not (yield dut.master.link_layer.ready):
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yield
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yield from mgr.update_packet_cnt.write(1)
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yield
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self.assertEqual((yield from mgr.packet_cnt_tx.read()), 0)
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self.assertEqual((yield from mgr.packet_cnt_rx.read()), 0)
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yield from mgr.request_echo.write(1)
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for i in range(15):
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yield
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yield from mgr.update_packet_cnt.write(1)
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yield
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self.assertEqual((yield from mgr.packet_cnt_tx.read()), 1)
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self.assertEqual((yield from mgr.packet_cnt_rx.read()), 1)
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run_simulation(dut, test(), self.clocks)
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