forked from M-Labs/artiq
drtio: break some RT features into manager, add echo request CSR
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1145a193dd
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@ -55,9 +55,12 @@ class DRTIOMaster(Module):
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self.submodules.rt_packets = rt_packets.RTPacketMaster(self.link_layer)
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self.submodules.rt_controller = rt_controller.RTController(
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self.rt_packets, channel_count, fine_ts_width)
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self.submodules.rt_manager = rt_controller.RTManager(self.rt_packets)
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def get_kernel_csrs(self):
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return self.rt_controller.get_kernel_csrs()
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def get_csrs(self):
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return self.link_layer.get_csrs() + self.rt_controller.get_csrs()
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return (self.link_layer.get_csrs() +
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self.rt_controller.get_csrs() +
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self.rt_manager.get_csrs())
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@ -22,25 +22,20 @@ class _CSRs(AutoCSR):
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self.o_reset_channel_status = CSR()
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self.o_wait = CSRStatus()
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self.err_present = CSR()
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self.err_code = CSRStatus(8)
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self.dbg_update_packet_cnt = CSR()
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self.dbg_packet_cnt_tx = CSRStatus(32)
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self.dbg_packet_cnt_rx = CSRStatus(32)
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class RTController(Module):
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def __init__(self, rt_packets, channel_count, fine_ts_width):
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self.kcsrs = KernelCSRs()
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self.csrs = _CSRs()
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# channel selection
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chan_sel = Signal(16)
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self.comb += chan_sel.eq(
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Mux(self.csrs.chan_sel_override_en.storage,
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self.csrs.chan_sel_override.storage,
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self.kcsrs.chan_sel.storage))
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# master RTIO counter and counter synchronization
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self.submodules.counter = RTIOCounter(64-fine_ts_width)
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self.sync += If(self.kcsrs.counter_update.re,
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self.kcsrs.counter.status.eq(self.counter.value_sys))
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@ -57,6 +52,7 @@ class RTController(Module):
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If(self.csrs.set_time.re, rt_packets.set_time_stb.eq(1))
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]
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# remote channel status cache
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fifo_spaces_mem = Memory(16, channel_count)
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fifo_spaces = fifo_spaces_mem.get_port(write_capable=True)
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self.specials += fifo_spaces_mem, fifo_spaces
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@ -64,6 +60,7 @@ class RTController(Module):
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last_timestamps = last_timestamps_mem.get_port(write_capable=True)
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self.specials += last_timestamps_mem, last_timestamps
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# common packet fields
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rt_packets_fifo_request = Signal()
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self.comb += [
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fifo_spaces.adr.eq(chan_sel),
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@ -172,22 +169,40 @@ class RTController(Module):
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)
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]
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# errors
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self.comb += [
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self.csrs.err_present.w.eq(rt_packets.error_not),
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rt_packets.error_not_ack.eq(self.csrs.err_present.re),
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self.csrs.err_code.status.eq(rt_packets.error_code)
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]
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# packet counters
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self.sync += \
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If(self.csrs.dbg_update_packet_cnt.re,
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self.csrs.dbg_packet_cnt_tx.status.eq(rt_packets.packet_cnt_tx),
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self.csrs.dbg_packet_cnt_rx.status.eq(rt_packets.packet_cnt_rx)
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)
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def get_kernel_csrs(self):
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return self.kcsrs.get_csrs()
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def get_csrs(self):
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return self.csrs.get_csrs()
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class RTManager(Module, AutoCSR):
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def __init__(self, rt_packets):
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self.request_echo = CSR()
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self.err_present = CSR()
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self.err_code = CSRStatus(8)
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self.update_packet_cnt = CSR()
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self.packet_cnt_tx = CSRStatus(32)
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self.packet_cnt_rx = CSRStatus(32)
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# # #
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self.comb += self.request_echo.w.eq(rt_packets.echo_stb)
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self.sync += [
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If(rt_packets.echo_ack, rt_packets.echo_stb.eq(0)),
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If(self.request_echo.re, rt_packets.echo_stb.eq(1))
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]
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self.comb += [
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self.err_present.w.eq(rt_packets.error_not),
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rt_packets.error_not_ack.eq(self.err_present.re),
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self.err_code.status.eq(rt_packets.error_code)
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]
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self.sync += \
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If(self.update_packet_cnt.re,
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self.packet_cnt_tx.status.eq(rt_packets.packet_cnt_tx),
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self.packet_cnt_rx.status.eq(rt_packets.packet_cnt_rx)
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)
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@ -59,6 +59,7 @@ class TestFullStack(unittest.TestCase):
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dut = DUT(2)
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kcsrs = dut.master.rt_controller.kcsrs
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csrs = dut.master.rt_controller.csrs
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mgr = dut.master.rt_manager
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ttl_changes = []
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correct_ttl_changes = [
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@ -157,7 +158,7 @@ class TestFullStack(unittest.TestCase):
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self.assertEqual(wlen, 2)
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def test_tsc_error():
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err_present = yield from csrs.err_present.read()
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err_present = yield from mgr.err_present.read()
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self.assertEqual(err_present, 0)
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yield from csrs.tsc_correction.write(10000000)
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yield from csrs.set_time.write(1)
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@ -167,13 +168,13 @@ class TestFullStack(unittest.TestCase):
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yield from write(0, 1)
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for i in range(10):
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yield
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err_present = yield from csrs.err_present.read()
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err_code = yield from csrs.err_code.read()
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err_present = yield from mgr.err_present.read()
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err_code = yield from mgr.err_code.read()
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self.assertEqual(err_present, 1)
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self.assertEqual(err_code, 3)
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yield from csrs.err_present.write(1)
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yield from mgr.err_present.write(1)
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yield
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err_present = yield from csrs.err_present.read()
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err_present = yield from mgr.err_present.read()
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self.assertEqual(err_present, 0)
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def test():
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