srenblad
/
artiq
forked from M-Labs/artiq
1
0
Fork 0
Code Pull Requests Activity

sayma: disable Urukul and Zotino for now 

Ultrascale I/Os are being a pain as usual and the SPI core won't compile.
This commit is contained in:
Sebastien Bourdeauducq 2018-07-17 20:08:21 +08:00
parent 8335085fd6
commit 4fdc20bb11
1 changed files with 4 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
artiq/gateware/targets/sayma_amc.py
View File

@ -474,12 +474,12 @@ class Master(MiniSoC, AMPSoC):
phy = ttl_simple.Output(s) phy = ttl_simple.Output(s)
self.submodules += phy self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy)) rtio_channels.append(rtio.Channel.from_phy(phy))
eem.Urukul.add_std(self, 1, 0, ttl_simple.Output, #eem.Urukul.add_std(self, 1, 0, ttl_simple.Output,
iostandard="LVDS") # iostandard="LVDS")
eem.DIO.add_std(self, 2, ttl_simple.Output, ttl_simple.Output, eem.DIO.add_std(self, 2, ttl_simple.Output, ttl_simple.Output,
iostandard="LVDS") iostandard="LVDS")
eem.Zotino.add_std(self, 3, ttl_simple.Output, #eem.Zotino.add_std(self, 3, ttl_simple.Output,
iostandard="LVDS") # iostandard="LVDS")
self.config["HAS_RTIO_LOG"] = None self.config["HAS_RTIO_LOG"] = None
self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels) self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)