From 4fdc20bb11762266147315f3bc8b576ec782dbf5 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Tue, 17 Jul 2018 20:08:21 +0800 Subject: [PATCH] sayma: disable Urukul and Zotino for now Ultrascale I/Os are being a pain as usual and the SPI core won't compile. --- artiq/gateware/targets/sayma_amc.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/artiq/gateware/targets/sayma_amc.py b/artiq/gateware/targets/sayma_amc.py index 219def0fe..91605cd50 100755 --- a/artiq/gateware/targets/sayma_amc.py +++ b/artiq/gateware/targets/sayma_amc.py @@ -474,12 +474,12 @@ class Master(MiniSoC, AMPSoC): phy = ttl_simple.Output(s) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) - eem.Urukul.add_std(self, 1, 0, ttl_simple.Output, - iostandard="LVDS") + #eem.Urukul.add_std(self, 1, 0, ttl_simple.Output, + # iostandard="LVDS") eem.DIO.add_std(self, 2, ttl_simple.Output, ttl_simple.Output, iostandard="LVDS") - eem.Zotino.add_std(self, 3, ttl_simple.Output, - iostandard="LVDS") + #eem.Zotino.add_std(self, 3, ttl_simple.Output, + # iostandard="LVDS") self.config["HAS_RTIO_LOG"] = None self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)