From 4d793d71496204884694ba8252ec76206aabbc19 Mon Sep 17 00:00:00 2001 From: David Nadlinger Date: Tue, 8 Jan 2019 02:08:13 +0000 Subject: [PATCH] ad9910: Truncate phase word to 16 bits This avoids overflowing into the asf portion of the register. --- artiq/coredevice/ad9910.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/artiq/coredevice/ad9910.py b/artiq/coredevice/ad9910.py index 160cf11d9..3e2ac0094 100644 --- a/artiq/coredevice/ad9910.py +++ b/artiq/coredevice/ad9910.py @@ -415,7 +415,8 @@ class AD9910: # is equivalent to an output pipeline latency. dt = int32(now_mu()) - int32(ref_time) pow_ += dt*ftw*self.sysclk_per_mu >> 16 - self.write64(_AD9910_REG_PROFILE0 + profile, (asf << 16) | pow_, ftw) + self.write64(_AD9910_REG_PROFILE0 + profile, + (asf << 16) | (pow_ & 0xffff), ftw) delay_mu(int64(self.io_update_delay)) self.cpld.io_update.pulse_mu(8) # assumes 8 mu > t_SYSCLK at_mu(now_mu() & ~0xf)