forked from M-Labs/artiq
ad9154: add mirrored bits
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@ -39,22 +39,38 @@ def AD9154_SDOACTIVE_SET(x: TInt32) -> TInt32:
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def AD9154_SDOACTIVE_GET(x: TInt32) -> TInt32:
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def AD9154_SDOACTIVE_GET(x: TInt32) -> TInt32:
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return (x >> 3) & 0x1
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return (x >> 3) & 0x1
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# default: 0x00, access: R
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# default: 0x00, access: R/W
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@portable
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def AD9154_SDOACTIVE_M_SET(x: TInt32) -> TInt32:
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return (x & 0x1) << 4
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@portable
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@portable
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def AD9154_SDOACTIVE_M_GET(x: TInt32) -> TInt32:
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def AD9154_SDOACTIVE_M_GET(x: TInt32) -> TInt32:
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return (x >> 4) & 0x1
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return (x >> 4) & 0x1
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# default: 0x00, access: R
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# default: 0x00, access: R/W
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@portable
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def AD9154_ADDRINC_M_SET(x: TInt32) -> TInt32:
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return (x & 0x1) << 5
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@portable
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@portable
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def AD9154_ADDRINC_M_GET(x: TInt32) -> TInt32:
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def AD9154_ADDRINC_M_GET(x: TInt32) -> TInt32:
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return (x >> 5) & 0x1
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return (x >> 5) & 0x1
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# default: 0x00, access: R
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# default: 0x00, access: R/W
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@portable
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def AD9154_LSBFIRST_M_SET(x: TInt32) -> TInt32:
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return (x & 0x1) << 6
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@portable
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@portable
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def AD9154_LSBFIRST_M_GET(x: TInt32) -> TInt32:
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def AD9154_LSBFIRST_M_GET(x: TInt32) -> TInt32:
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return (x >> 6) & 0x1
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return (x >> 6) & 0x1
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# default: 0x00, access: R
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# default: 0x00, access: R/W
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@portable
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def AD9154_SOFTRESET_M_SET(x: TInt32) -> TInt32:
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return (x & 0x1) << 7
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@portable
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@portable
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def AD9154_SOFTRESET_M_GET(x: TInt32) -> TInt32:
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def AD9154_SOFTRESET_M_GET(x: TInt32) -> TInt32:
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return (x >> 7) & 0x1
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return (x >> 7) & 0x1
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