From 4c7c479c94a45acc4e29ce5a9bd6a668945cbc56 Mon Sep 17 00:00:00 2001 From: Robert Jordens Date: Thu, 13 Oct 2016 15:02:18 +0200 Subject: [PATCH] ad9154: add mirrored bits --- artiq/coredevice/ad9154_reg.py | 24 ++++++++++++++++++++---- 1 file changed, 20 insertions(+), 4 deletions(-) diff --git a/artiq/coredevice/ad9154_reg.py b/artiq/coredevice/ad9154_reg.py index 6993745c1..a7d414e96 100644 --- a/artiq/coredevice/ad9154_reg.py +++ b/artiq/coredevice/ad9154_reg.py @@ -39,22 +39,38 @@ def AD9154_SDOACTIVE_SET(x: TInt32) -> TInt32: def AD9154_SDOACTIVE_GET(x: TInt32) -> TInt32: return (x >> 3) & 0x1 -# default: 0x00, access: R +# default: 0x00, access: R/W +@portable +def AD9154_SDOACTIVE_M_SET(x: TInt32) -> TInt32: + return (x & 0x1) << 4 + @portable def AD9154_SDOACTIVE_M_GET(x: TInt32) -> TInt32: return (x >> 4) & 0x1 -# default: 0x00, access: R +# default: 0x00, access: R/W +@portable +def AD9154_ADDRINC_M_SET(x: TInt32) -> TInt32: + return (x & 0x1) << 5 + @portable def AD9154_ADDRINC_M_GET(x: TInt32) -> TInt32: return (x >> 5) & 0x1 -# default: 0x00, access: R +# default: 0x00, access: R/W +@portable +def AD9154_LSBFIRST_M_SET(x: TInt32) -> TInt32: + return (x & 0x1) << 6 + @portable def AD9154_LSBFIRST_M_GET(x: TInt32) -> TInt32: return (x >> 6) & 0x1 -# default: 0x00, access: R +# default: 0x00, access: R/W +@portable +def AD9154_SOFTRESET_M_SET(x: TInt32) -> TInt32: + return (x & 0x1) << 7 + @portable def AD9154_SOFTRESET_M_GET(x: TInt32) -> TInt32: return (x >> 7) & 0x1