forked from M-Labs/artiq
coredevice/core: remove default period
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cdcb57effe
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4b5c10b641
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@ -47,7 +47,7 @@ class Core:
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external RTIO clock input instead of using its internal oscillator.
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:param comm_device: name of the device used for communications.
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"""
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def __init__(self, dmgr, ref_period=8*ns, external_clock=False, comm_device="comm"):
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def __init__(self, dmgr, ref_period, external_clock=False, comm_device="comm"):
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self.ref_period = ref_period
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self.external_clock = external_clock
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self.comm = dmgr.get(comm_device)
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