srenblad
/
artiq
forked from M-Labs/artiq
1
0
Fork 0
Code Pull Requests Activity

suservo: use BUFIO/BUFH for ADC

This commit is contained in:
Robert Jördens 2018-04-23 18:24:22 +00:00
parent e36deab0a8
commit 4903eb074c
1 changed files with 9 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
artiq/gateware/suservo/adc_ser.py
View File

@ -119,9 +119,16 @@ class ADC(Module, DiffMixin):
except AttributeError: except AttributeError:
sck_en_ret = 1 sck_en_ret = 1
self.clock_domains.cd_ret = ClockDomain("ret", reset_less=True) self.clock_domains.cd_ret = ClockDomain("ret", reset_less=True)
clkout = self._diff(pads, "clkout")
clkout_fabric = Signal()
clkout_io = Signal()
self.specials += [
Instance("BUFH", i_I=clkout, o_O=clkout_fabric),
Instance("BUFIO", i_I=clkout, o_O=clkout_io)
]
self.comb += [ self.comb += [
# falling clkout makes two bits available # falling clkout makes two bits available
self.cd_ret.clk.eq(~self._diff(pads, "clkout")), self.cd_ret.clk.eq(~clkout_fabric)
] ]
k = p.channels//p.lanes k = p.channels//p.lanes
assert 2*t_read == k*p.width assert 2*t_read == k*p.width
@ -130,7 +137,7 @@ class ADC(Module, DiffMixin):
sdo_sr1 = Signal(t_read - 1) sdo_sr1 = Signal(t_read - 1)
sdo_ddr = Signal(2) sdo_ddr = Signal(2)
self.specials += io.DDRInput(sdo, sdo_ddr[1], sdo_ddr[0], self.specials += io.DDRInput(sdo, sdo_ddr[1], sdo_ddr[0],
self.cd_ret.clk) ~clkout_io)
self.sync.ret += [ self.sync.ret += [
If(self.reading & sck_en_ret, If(self.reading & sck_en_ret,
sdo_sr0.eq(Cat(sdo_ddr[0], sdo_sr0)), sdo_sr0.eq(Cat(sdo_ddr[0], sdo_sr0)),