From 46c044099c9d7caf7f2886c828e6d5d5055c7984 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Wed, 27 Jun 2018 17:36:13 +0800 Subject: [PATCH] hmc7043,satman: verify alignment of SYSREF slips --- artiq/firmware/libboard_artiq/ad9154.rs | 2 +- artiq/firmware/libboard_artiq/hmc830_7043.rs | 17 ++++++++++------- artiq/firmware/satman/main.rs | 5 ++++- 3 files changed, 15 insertions(+), 9 deletions(-) diff --git a/artiq/firmware/libboard_artiq/ad9154.rs b/artiq/firmware/libboard_artiq/ad9154.rs index a1549b601..4b0e11be1 100644 --- a/artiq/firmware/libboard_artiq/ad9154.rs +++ b/artiq/firmware/libboard_artiq/ad9154.rs @@ -769,7 +769,7 @@ pub fn init(sysref_phase_fpga: u16, sysref_phase_dac: u16) { // the HMC7043 input clock (which defines slip resolution) // is 2x the DAC clock, so there are two possible phases from // the divider states. This deterministically selects one. - hmc7043::sysref_rtio_align(sysref_phase_fpga); + hmc7043::sysref_rtio_align(sysref_phase_fpga, 1); for dacno in 0..csr::AD9154.len() { // We assume DCLK and SYSREF traces are matched on the PCB diff --git a/artiq/firmware/libboard_artiq/hmc830_7043.rs b/artiq/firmware/libboard_artiq/hmc830_7043.rs index e41ae9361..1dba30034 100644 --- a/artiq/firmware/libboard_artiq/hmc830_7043.rs +++ b/artiq/firmware/libboard_artiq/hmc830_7043.rs @@ -158,13 +158,13 @@ pub mod hmc7043 { use board_misoc::{csr, clock}; // All frequencies assume 1.2GHz HMC830 output - const DAC_CLK_DIV: u32 = 2; // 600MHz - const FPGA_CLK_DIV: u32 = 8; // 150MHz - const SYSREF_DIV: u32 = 128; // 9.375MHz - const HMC_SYSREF_DIV: u32 = SYSREF_DIV*8; // 1.171875MHz (must be <= 4MHz) + pub const DAC_CLK_DIV: u16 = 2; // 600MHz + pub const FPGA_CLK_DIV: u16 = 8; // 150MHz + pub const SYSREF_DIV: u16 = 128; // 9.375MHz + pub const HMC_SYSREF_DIV: u16 = SYSREF_DIV*8; // 1.171875MHz (must be <= 4MHz) // enabled, divider, output config - const OUTPUT_CONFIG: [(bool, u32, u8); 14] = [ + const OUTPUT_CONFIG: [(bool, u16, u8); 14] = [ (true, DAC_CLK_DIV, 0x08), // 0: DAC2_CLK (true, SYSREF_DIV, 0x08), // 1: DAC2_SYSREF (true, DAC_CLK_DIV, 0x08), // 2: DAC1_CLK @@ -355,7 +355,7 @@ pub mod hmc7043 { unsafe { csr::sysref_sampler::sample_result_read() == 1 } } - pub fn sysref_rtio_align(phase_offset: u16) { + pub fn sysref_rtio_align(phase_offset: u16, expected_align: u16) { info!("aligning SYSREF with RTIO..."); let mut slips0 = 0; @@ -380,7 +380,10 @@ pub mod hmc7043 { break; } } - info!(" ...done ({}/{} slips), verifying timing margin", slips0, slips1); + info!(" ...done ({}/{} slips)", slips0, slips1); + if (slips0 + slips1) % expected_align != 0 { + error!(" unexpected slip alignment"); + } let mut margin_minus = None; for d in 0..phase_offset { diff --git a/artiq/firmware/satman/main.rs b/artiq/firmware/satman/main.rs index 4e3a1a4c5..4ce7b2963 100644 --- a/artiq/firmware/satman/main.rs +++ b/artiq/firmware/satman/main.rs @@ -298,7 +298,10 @@ pub extern fn main() -> i32 { #[cfg(has_hmc830_7043)] { if drtio_tsc_loaded() { - hmc830_7043::hmc7043::sysref_rtio_align(SYSREF_PHASE_FPGA); + // Expected alignment: 1 RTIO clock period + hmc830_7043::hmc7043::sysref_rtio_align( + SYSREF_PHASE_FPGA, + hmc830_7043::hmc7043::FPGA_CLK_DIV); } } }