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phaser: update stpl

This commit is contained in:
Robert Jördens 2016-10-12 14:22:21 +02:00
parent 5f737bef76
commit 466d1e8304
1 changed files with 38 additions and 33 deletions
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17
artiq/examples/phaser/repository/test_ad9154_stpl.py
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@ -1,4 +1,4 @@
import time from jesd204b.transport import seed_to_data
from artiq.coredevice.ad9154_reg import * from artiq.coredevice.ad9154_reg import *
from artiq.experiment import * from artiq.experiment import *
@ -10,11 +10,16 @@ class Test(EnvExperiment):
self.setattr_device("ad9154") self.setattr_device("ad9154")
def run(self): def run(self):
self.stpl() self.ad9154.jesd_stpl(0)
def stpl(self):
# short transport layer test # short transport layer test
for i, data in enumerate([0x0123, 0x4567, 0x89ab, 0xcdef]): for i in range(4):
data = seed_to_data(i << 8, True)
fail = self.stpl(i, data)
print("channel", i, "FAIL" if fail else "PASS")
self.ad9154.jesd_stpl(0)
@kernel
def stpl(self, i, data):
# select dac # select dac
self.ad9154.dac_write(AD9154_SHORT_TPL_TEST_0, self.ad9154.dac_write(AD9154_SHORT_TPL_TEST_0,
AD9154_SHORT_TPL_TEST_EN_SET(0) | AD9154_SHORT_TPL_TEST_EN_SET(0) |
@ -42,4 +47,4 @@ class Test(EnvExperiment):
AD9154_SHORT_TPL_TEST_RESET_SET(0) | AD9154_SHORT_TPL_TEST_RESET_SET(0) |
AD9154_SHORT_TPL_DAC_SEL_SET(i) | AD9154_SHORT_TPL_DAC_SEL_SET(i) |
AD9154_SHORT_TPL_SP_SEL_SET(0)) AD9154_SHORT_TPL_SP_SEL_SET(0))
print("c{:d}: {:d}".format(i, self.ad9154.dac_read(AD9154_SHORT_TPL_TEST_3))) return self.ad9154.dac_read(AD9154_SHORT_TPL_TEST_3)