diff --git a/artiq/examples/phaser/repository/test_ad9154_stpl.py b/artiq/examples/phaser/repository/test_ad9154_stpl.py
index bc5cc40c4..3dc3acda0 100644
--- a/artiq/examples/phaser/repository/test_ad9154_stpl.py
+++ b/artiq/examples/phaser/repository/test_ad9154_stpl.py
@@ -1,4 +1,4 @@
-import time
+from jesd204b.transport import seed_to_data
 
 from artiq.coredevice.ad9154_reg import *
 from artiq.experiment import *
@@ -10,36 +10,41 @@ class Test(EnvExperiment):
         self.setattr_device("ad9154")
 
     def run(self):
-        self.stpl()
-
-    def stpl(self):
+        self.ad9154.jesd_stpl(0)
         # short transport layer test
-        for i, data in enumerate([0x0123, 0x4567, 0x89ab, 0xcdef]):
-            # select dac
-            self.ad9154.dac_write(AD9154_SHORT_TPL_TEST_0,
-                AD9154_SHORT_TPL_TEST_EN_SET(0) |
-                AD9154_SHORT_TPL_TEST_RESET_SET(0) |
-                AD9154_SHORT_TPL_DAC_SEL_SET(i) |
-                AD9154_SHORT_TPL_SP_SEL_SET(0))
-            # set expected value
-            self.ad9154.dac_write(AD9154_SHORT_TPL_TEST_2, data & 0xff)
-            self.ad9154.dac_write(AD9154_SHORT_TPL_TEST_1, (data & 0xff00) >> 8)
-            # enable stpl
-            self.ad9154.dac_write(AD9154_SHORT_TPL_TEST_0,
-                AD9154_SHORT_TPL_TEST_EN_SET(1) |
-                AD9154_SHORT_TPL_TEST_RESET_SET(0) |
-                AD9154_SHORT_TPL_DAC_SEL_SET(i) |
-                AD9154_SHORT_TPL_SP_SEL_SET(0))
-            # reset stpl
-            self.ad9154.dac_write(AD9154_SHORT_TPL_TEST_0,
-                AD9154_SHORT_TPL_TEST_EN_SET(1) |
-                AD9154_SHORT_TPL_TEST_RESET_SET(1) |
-                AD9154_SHORT_TPL_DAC_SEL_SET(i) |
-                AD9154_SHORT_TPL_SP_SEL_SET(0))
-            # release reset stpl
-            self.ad9154.dac_write(AD9154_SHORT_TPL_TEST_0,
-                AD9154_SHORT_TPL_TEST_EN_SET(1) |
-                AD9154_SHORT_TPL_TEST_RESET_SET(0) |
-                AD9154_SHORT_TPL_DAC_SEL_SET(i) |
-                AD9154_SHORT_TPL_SP_SEL_SET(0))
-            print("c{:d}: {:d}".format(i, self.ad9154.dac_read(AD9154_SHORT_TPL_TEST_3)))
+        for i in range(4):
+            data = seed_to_data(i << 8, True)
+            fail = self.stpl(i, data)
+            print("channel", i, "FAIL" if fail else "PASS")
+        self.ad9154.jesd_stpl(0)
+
+    @kernel
+    def stpl(self, i, data):
+        # select dac
+        self.ad9154.dac_write(AD9154_SHORT_TPL_TEST_0,
+            AD9154_SHORT_TPL_TEST_EN_SET(0) |
+            AD9154_SHORT_TPL_TEST_RESET_SET(0) |
+            AD9154_SHORT_TPL_DAC_SEL_SET(i) |
+            AD9154_SHORT_TPL_SP_SEL_SET(0))
+        # set expected value
+        self.ad9154.dac_write(AD9154_SHORT_TPL_TEST_2, data & 0xff)
+        self.ad9154.dac_write(AD9154_SHORT_TPL_TEST_1, (data & 0xff00) >> 8)
+        # enable stpl
+        self.ad9154.dac_write(AD9154_SHORT_TPL_TEST_0,
+            AD9154_SHORT_TPL_TEST_EN_SET(1) |
+            AD9154_SHORT_TPL_TEST_RESET_SET(0) |
+            AD9154_SHORT_TPL_DAC_SEL_SET(i) |
+            AD9154_SHORT_TPL_SP_SEL_SET(0))
+        # reset stpl
+        self.ad9154.dac_write(AD9154_SHORT_TPL_TEST_0,
+            AD9154_SHORT_TPL_TEST_EN_SET(1) |
+            AD9154_SHORT_TPL_TEST_RESET_SET(1) |
+            AD9154_SHORT_TPL_DAC_SEL_SET(i) |
+            AD9154_SHORT_TPL_SP_SEL_SET(0))
+        # release reset stpl
+        self.ad9154.dac_write(AD9154_SHORT_TPL_TEST_0,
+            AD9154_SHORT_TPL_TEST_EN_SET(1) |
+            AD9154_SHORT_TPL_TEST_RESET_SET(0) |
+            AD9154_SHORT_TPL_DAC_SEL_SET(i) |
+            AD9154_SHORT_TPL_SP_SEL_SET(0))
+        return self.ad9154.dac_read(AD9154_SHORT_TPL_TEST_3)