firmware: simplify SYSREF DRTIO alignment

artiq/firmware/libboard_artiq/hmc830_7043.rs

@@ -156,10 +156,10 @@ pub mod hmc7043 {
     use board_misoc::{csr, clock};
 
     // All frequencies assume 1.2GHz HMC830 output
-    pub const DAC_CLK_DIV: u16 = 2;               // 600MHz
+    const DAC_CLK_DIV: u16 = 2;               // 600MHz
-    pub const FPGA_CLK_DIV: u16 = 8;              // 150MHz
+    const FPGA_CLK_DIV: u16 = 8;              // 150MHz
-    pub const SYSREF_DIV: u16 = 128;              // 9.375MHz
+    const SYSREF_DIV: u16 = 128;              // 9.375MHz
-    pub const HMC_SYSREF_DIV: u16 = SYSREF_DIV*8; // 1.171875MHz (must be <= 4MHz)
+    const HMC_SYSREF_DIV: u16 = SYSREF_DIV*8; // 1.171875MHz (must be <= 4MHz)
 
     // enabled, divider, output config
     const OUTPUT_CONFIG: [(bool, u16, u8); 14] = [

artiq/firmware/libboard_artiq/jesd204sync.rs

@@ -67,8 +67,8 @@ fn sysref_cal_fpga() -> Result<u16, &'static str> {
     return Err("failed to reach 1->0 transition with fine delay");
 }
 
-fn sysref_rtio_align(phase_offset: u16, expected_align: u16) -> Result<(), &'static str> {
+fn sysref_rtio_align(phase_offset: u16) -> Result<(), &'static str> {
-    // This needs to take place once before DAC SYSREF scan, as
+    // This needs to take place before DAC SYSREF scan, as
     // the HMC7043 input clock (which defines slip resolution)
     // is 2x the DAC clock, so there are two possible phases from
     // the divider states. This deterministically selects one.
@@ -96,9 +96,6 @@ fn sysref_rtio_align(phase_offset: u16, expected_align: u16) -> Result<(), &'sta
         }
     }
     info!("  ...done ({}/{} slips)", slips0, slips1);
-    if (slips0 + slips1) % expected_align != 0 {
-        return Err("unexpected slip alignment");
-    }
 
     let mut margin_minus = None;
     for d in 0..phase_offset {
@@ -127,7 +124,7 @@ fn sysref_rtio_align(phase_offset: u16, expected_align: u16) -> Result<(), &'sta
     Ok(())
 }
 
-pub fn sysref_auto_rtio_align(expected_align: u16) -> Result<(), &'static str> {
+pub fn sysref_auto_rtio_align() -> Result<(), &'static str> {
     let entry = config::read_str("sysref_phase_fpga", |r| r.map(|s| s.parse()));
     let phase_offset = match entry {
         Ok(Ok(phase)) => phase,
@@ -139,7 +136,7 @@ pub fn sysref_auto_rtio_align(expected_align: u16) -> Result<(), &'static str> {
             phase
         }
     };
-    sysref_rtio_align(phase_offset, expected_align)
+    sysref_rtio_align(phase_offset)
 }
 
 fn sysref_cal_dac(dacno: u8) -> Result<u16, &'static str> {

artiq/firmware/runtime/main.rs

@@ -112,7 +112,7 @@ fn startup() {
     {
         board_artiq::ad9154::jesd_unreset();
         board_artiq::ad9154::init();
-        if let Err(e) = board_artiq::jesd204sync::sysref_auto_rtio_align(1) {
+        if let Err(e) = board_artiq::jesd204sync::sysref_auto_rtio_align() {
             error!("failed to align SYSREF at FPGA: {}", e);
         }
         if let Err(e) = board_artiq::jesd204sync::sysref_auto_dac_align() {

artiq/firmware/satman/main.rs

@@ -274,7 +274,10 @@ pub extern fn main() -> i32 {
     }
 
     #[cfg(has_ad9154)]
-    let mut ad9154_initialized = false;
+    {
+        board_artiq::ad9154::jesd_unreset();
+        board_artiq::ad9154::init();
+    }
     #[cfg(has_allaki_atts)]
     board_artiq::hmc542::program_all(8/*=4dB*/);
 
@@ -285,34 +288,21 @@ pub extern fn main() -> i32 {
         info!("link is up, switching to recovered clock");
         si5324::siphaser::select_recovered_clock(true).expect("failed to switch clocks");
         si5324::siphaser::calibrate_skew(SIPHASER_PHASE).expect("failed to calibrate skew");
-        #[cfg(has_ad9154)]
-        {
-            if !ad9154_initialized {
-                board_artiq::ad9154::jesd_unreset();
-                board_artiq::ad9154::init();
-                if let Err(e) = board_artiq::jesd204sync::sysref_auto_rtio_align(1) {
-                    error!("failed to align SYSREF at FPGA: {}", e);
-                }
-                if let Err(e) = board_artiq::jesd204sync::sysref_auto_dac_align() {
-                    error!("failed to align SYSREF at DAC: {}", e);
-                }
-                ad9154_initialized = true;
-            }
-        }
         drtioaux::reset(0);
         drtio_reset(false);
         drtio_reset_phy(false);
         while drtio_link_rx_up() {
             process_errors();
             process_aux_packets();
-            #[cfg(has_hmc830_7043)]
+            #[cfg(has_ad9154)]
             {
                 if drtio_tsc_loaded() {
-                    // Expected alignment: 1 RTIO clock period
+                    if let Err(e) = board_artiq::jesd204sync::sysref_auto_rtio_align() {
-                    if let Err(e) = board_artiq::jesd204sync::sysref_auto_rtio_align(
-                            hmc830_7043::hmc7043::FPGA_CLK_DIV) {
                         error!("failed to align SYSREF at FPGA: {}", e);
                     }
+                    if let Err(e) = board_artiq::jesd204sync::sysref_auto_dac_align() {
+                        error!("failed to align SYSREF at DAC: {}", e);
+                    }
                 }
             }
         }