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soc,runtime: define RTIO FUD channel number in targets

This commit is contained in:
Sebastien Bourdeauducq 2015-04-09 00:35:11 +08:00
parent efd1c24ed7
commit 44304a33b2
4 changed files with 6 additions and 4 deletions
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2
soc/runtime/rtio.c
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@ -91,8 +91,6 @@ int rtio_pileup_count(int channel)
return r; return r;
} }
#define RTIO_FUD_CHANNEL 8
void rtio_fud_sync(void) void rtio_fud_sync(void)
{ {
while(rtio_get_counter() < previous_fud_end_time); while(rtio_get_counter() < previous_fud_end_time);

1
soc/targets/artiq_kc705.py
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@ -52,6 +52,7 @@ class _Peripherals(BaseSoC):
rtio_ins = [platform.request("pmt") for i in range(2)] rtio_ins = [platform.request("pmt") for i in range(2)]
rtio_outs = [platform.request("ttl", i) for i in range(16)] rtio_outs = [platform.request("ttl", i) for i in range(16)]
rtio_outs.append(platform.request("user_led", 2)) rtio_outs.append(platform.request("user_led", 2))
self.add_constant("RTIO_FUD_CHANNEL", len(rtio_ins) + len(rtio_outs))
rtio_outs.append(fud) rtio_outs.append(fud)
self.submodules.rtiocrg = _RTIOCRG(platform, self.crg.pll_sys) self.submodules.rtiocrg = _RTIOCRG(platform, self.crg.pll_sys)

3
soc/targets/artiq_pipistrello.py
View File

@ -69,9 +69,10 @@ class _Peripherals(BaseSoC):
rtio_ins = [platform.request("pmt", i) for i in range(2)] rtio_ins = [platform.request("pmt", i) for i in range(2)]
rtio_ins += [platform.request("xtrig", 0)] rtio_ins += [platform.request("xtrig", 0)]
rtio_outs = [platform.request("ttl", i) for i in range(16)] rtio_outs = [platform.request("ttl", i) for i in range(16)]
rtio_outs += [fud]
rtio_outs += [platform.request("ext_led", 0)] rtio_outs += [platform.request("ext_led", 0)]
rtio_outs += [platform.request("user_led", i) for i in range(2, 5)] rtio_outs += [platform.request("user_led", i) for i in range(2, 5)]
self.add_constant("RTIO_FUD_CHANNEL", len(rtio_ins) + len(rtio_outs))
rtio_outs.append(fud)
self.submodules.rtiocrg = _RTIOCRG(platform) self.submodules.rtiocrg = _RTIOCRG(platform)
self.submodules.rtiophy = rtio.phy.SimplePHY( self.submodules.rtiophy = rtio.phy.SimplePHY(

4
soc/targets/artiq_ppro.py
View File

@ -78,7 +78,9 @@ class UP(BaseSoC):
platform.request("ttl_h_tx_en").eq(1) platform.request("ttl_h_tx_en").eq(1)
] ]
rtio_ins = [platform.request("pmt") for i in range(2)] rtio_ins = [platform.request("pmt") for i in range(2)]
rtio_outs = [platform.request("ttl", i) for i in range(5)] + [fud] rtio_outs = [platform.request("ttl", i) for i in range(5)]
self.add_constant("RTIO_FUD_CHANNEL", len(rtio_ins) + len(rtio_outs))
rtio_outs.append(fud)
self.submodules.rtiocrg = _RTIOMiniCRG(platform) self.submodules.rtiocrg = _RTIOMiniCRG(platform)
self.submodules.rtiophy = rtio.phy.SimplePHY( self.submodules.rtiophy = rtio.phy.SimplePHY(