From 44304a33b24ca420b5ae00ec5a408dbebcec0cb2 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Thu, 9 Apr 2015 00:35:11 +0800 Subject: [PATCH] soc,runtime: define RTIO FUD channel number in targets --- soc/runtime/rtio.c | 2 -- soc/targets/artiq_kc705.py | 1 + soc/targets/artiq_pipistrello.py | 3 ++- soc/targets/artiq_ppro.py | 4 +++- 4 files changed, 6 insertions(+), 4 deletions(-) diff --git a/soc/runtime/rtio.c b/soc/runtime/rtio.c index 300cfcc04..441f062ee 100644 --- a/soc/runtime/rtio.c +++ b/soc/runtime/rtio.c @@ -91,8 +91,6 @@ int rtio_pileup_count(int channel) return r; } -#define RTIO_FUD_CHANNEL 8 - void rtio_fud_sync(void) { while(rtio_get_counter() < previous_fud_end_time); diff --git a/soc/targets/artiq_kc705.py b/soc/targets/artiq_kc705.py index 1c4edfa46..e56f1dc59 100644 --- a/soc/targets/artiq_kc705.py +++ b/soc/targets/artiq_kc705.py @@ -52,6 +52,7 @@ class _Peripherals(BaseSoC): rtio_ins = [platform.request("pmt") for i in range(2)] rtio_outs = [platform.request("ttl", i) for i in range(16)] rtio_outs.append(platform.request("user_led", 2)) + self.add_constant("RTIO_FUD_CHANNEL", len(rtio_ins) + len(rtio_outs)) rtio_outs.append(fud) self.submodules.rtiocrg = _RTIOCRG(platform, self.crg.pll_sys) diff --git a/soc/targets/artiq_pipistrello.py b/soc/targets/artiq_pipistrello.py index 88ba7e35b..02b889022 100644 --- a/soc/targets/artiq_pipistrello.py +++ b/soc/targets/artiq_pipistrello.py @@ -69,9 +69,10 @@ class _Peripherals(BaseSoC): rtio_ins = [platform.request("pmt", i) for i in range(2)] rtio_ins += [platform.request("xtrig", 0)] rtio_outs = [platform.request("ttl", i) for i in range(16)] - rtio_outs += [fud] rtio_outs += [platform.request("ext_led", 0)] rtio_outs += [platform.request("user_led", i) for i in range(2, 5)] + self.add_constant("RTIO_FUD_CHANNEL", len(rtio_ins) + len(rtio_outs)) + rtio_outs.append(fud) self.submodules.rtiocrg = _RTIOCRG(platform) self.submodules.rtiophy = rtio.phy.SimplePHY( diff --git a/soc/targets/artiq_ppro.py b/soc/targets/artiq_ppro.py index 1d80952de..f585c8815 100644 --- a/soc/targets/artiq_ppro.py +++ b/soc/targets/artiq_ppro.py @@ -78,7 +78,9 @@ class UP(BaseSoC): platform.request("ttl_h_tx_en").eq(1) ] rtio_ins = [platform.request("pmt") for i in range(2)] - rtio_outs = [platform.request("ttl", i) for i in range(5)] + [fud] + rtio_outs = [platform.request("ttl", i) for i in range(5)] + self.add_constant("RTIO_FUD_CHANNEL", len(rtio_ins) + len(rtio_outs)) + rtio_outs.append(fud) self.submodules.rtiocrg = _RTIOMiniCRG(platform) self.submodules.rtiophy = rtio.phy.SimplePHY(