compiler: switch to upstream llvmlite and RISC-V target

artiq/compiler/targets.py

@@ -1,6 +1,6 @@
 import os, sys, tempfile, subprocess, io
 from artiq.compiler import types, ir
-from llvmlite_artiq import ir as ll, binding as llvm
+from llvmlite import ir as ll, binding as llvm
 
 llvm.initialize()
 llvm.initialize_all_targets()
@@ -67,7 +67,7 @@ class Target:
     generated by the ARTIQ compiler will be deployed.
 
     :var triple: (string)
-        LLVM target triple, e.g. ``"or1k"``
+        LLVM target triple, e.g. ``"riscv32"``
     :var data_layout: (string)
         LLVM target data layout, e.g. ``"E-m:e-p:32:32-i64:32-f64:32-v64:32-v128:32-a:0:32-n32"``
     :var features: (list of string)
@@ -255,19 +255,18 @@ class NativeTarget(Target):
         assert host_data_layout[0] in "eE"
         self.little_endian = host_data_layout[0] == "e"
 
-class OR1KTarget(Target):
-    triple = "or1k-linux"
-    data_layout = "E-m:e-p:32:32-i8:8:8-i16:16:16-i64:32:32-" \
-                  "f64:32:32-v64:32:32-v128:32:32-a0:0:32-n32"
-    features = ["mul", "div", "ffl1", "cmov", "addc"]
+class RISCVTarget(Target):
+    triple = "riscv32-unknown-linux"
+    data_layout = "e-m:e-p:32:32-i64:64-n32-S128"
+    features = []
     print_function = "core_log"
     little_endian = False
     now_pinning = True
 
-    tool_ld = "or1k-linux-ld"
-    tool_strip = "or1k-linux-strip"
-    tool_addr2line = "or1k-linux-addr2line"
-    tool_cxxfilt = "or1k-linux-c++filt"
+    tool_ld = "ld.lld"
+    tool_strip = "llvm-strip"
+    tool_addr2line = "llvm-addr2line"
+    tool_cxxfilt = "llvm-cxxfilt"
 
 class CortexA9Target(Target):
     triple = "armv7-unknown-linux-gnueabihf"

artiq/compiler/testbench/jit.py

@@ -1,6 +1,6 @@
 import os, sys, fileinput, ctypes
 from pythonparser import diagnostic
-from llvmlite_artiq import binding as llvm
+from llvmlite import binding as llvm
 from ..module import Module, Source
 from ..targets import NativeTarget
 

artiq/compiler/testbench/llvmgen.py

@@ -1,6 +1,6 @@
 import sys, fileinput
 from pythonparser import diagnostic
-from llvmlite_artiq import ir as ll
+from llvmlite import ir as ll
 from ..module import Module, Source
 from ..targets import NativeTarget
 

artiq/compiler/testbench/perf.py

@@ -1,7 +1,7 @@
 import sys, os
 from pythonparser import diagnostic
 from ..module import Module, Source
-from ..targets import OR1KTarget
+from ..targets import RISCVTarget
 from . import benchmark
 
 def main():
@@ -30,7 +30,7 @@ def main():
     benchmark(lambda: Module(source),
               "ARTIQ transforms and validators")
 
-    benchmark(lambda: OR1KTarget().compile_and_link([module]),
+    benchmark(lambda: RISCVTarget().compile_and_link([module]),
               "LLVM optimization and linking")
 
 if __name__ == "__main__":

artiq/compiler/testbench/perf_embedding.py

@@ -5,7 +5,7 @@ from ...master.databases import DeviceDB, DatasetDB
 from ...master.worker_db import DeviceManager, DatasetManager
 from ..module import Module
 from ..embedding import Stitcher
-from ..targets import OR1KTarget
+from ..targets import RISCVTarget
 from . import benchmark
 
 
@@ -45,7 +45,7 @@ def main():
 
     stitcher = embed()
     module = Module(stitcher)
-    target = OR1KTarget()
+    target = RISCVTarget()
     llvm_ir = target.compile(module)
     elf_obj = target.assemble(llvm_ir)
     elf_shlib = target.link([elf_obj])

artiq/compiler/testbench/shlib.py

@@ -1,7 +1,7 @@
 import sys, os
 from pythonparser import diagnostic
 from ..module import Module, Source
-from ..targets import OR1KTarget
+from ..targets import RISCVTarget
 
 def main():
     if not len(sys.argv) > 1:
@@ -20,7 +20,7 @@ def main():
     for filename in sys.argv[1:]:
         modules.append(Module(Source.from_filename(filename, engine=engine)))
 
-    llobj = OR1KTarget().compile_and_link(modules)
+    llobj = RISCVTarget().compile_and_link(modules)
 
     basename, ext = os.path.splitext(sys.argv[-1])
     with open(basename + ".so", "wb") as f:

artiq/compiler/transforms/llvm_ir_generator.py

@@ -6,7 +6,7 @@ into LLVM intermediate representation.
 import os, re, types as pytypes, numpy
 from collections import defaultdict
 from pythonparser import ast, diagnostic
-from llvmlite_artiq import ir as ll, binding as llvm
+from llvmlite import ir as ll, binding as llvm
 from ...language import core as language_core
 from .. import types, builtins, ir
 from ..embedding import SpecializedFunction

artiq/coredevice/core.py

@@ -11,7 +11,7 @@ from artiq.language.units import *
 
 from artiq.compiler.module import Module
 from artiq.compiler.embedding import Stitcher
-from artiq.compiler.targets import OR1KTarget, CortexA9Target
+from artiq.compiler.targets import RISCVTarget, CortexA9Target
 
 from artiq.coredevice.comm_kernel import CommKernel, CommKernelDummy
 # Import for side effects (creating the exception classes).
@@ -71,11 +71,11 @@ class Core:
         "core", "ref_period", "coarse_ref_period", "ref_multiplier",
     }
 
-    def __init__(self, dmgr, host, ref_period, ref_multiplier=8, target="or1k"):
+    def __init__(self, dmgr, host, ref_period, ref_multiplier=8, target="riscv"):
         self.ref_period = ref_period
         self.ref_multiplier = ref_multiplier
-        if target == "or1k":
-            self.target_cls = OR1KTarget
+        if target == "riscv":
+            self.target_cls = RISCVTarget
         elif target == "cortexa9":
             self.target_cls = CortexA9Target
         else:

artiq/frontend/artiq_ddb_template.py

@@ -15,7 +15,7 @@ def process_header(output, description):
         raise NotImplementedError
 
     cpu_target = {
-        "kasli": "or1k",
+        "kasli": "riscv",
         "kasli_soc": "cortexa9"
     }[description["target"]]
 

artiq/frontend/artiq_run.py

@@ -10,7 +10,7 @@ from collections import defaultdict
 
 import h5py
 
-from llvmlite_artiq import binding as llvm
+from llvmlite import binding as llvm
 
 from sipyco import common_args
 

doc/manual/conf.py

@@ -37,7 +37,7 @@ mock_modules = ["artiq.gui.waitingspinnerwidget",
                 "qasync", "pyqtgraph", "matplotlib",
                 "numpy", "dateutil", "dateutil.parser", "prettytable", "PyQt5",
                 "h5py", "serial", "scipy", "scipy.interpolate",
-                "llvmlite_artiq", "Levenshtein", "pythonparser",
+                "llvmlite", "Levenshtein", "pythonparser",
                 "sipyco", "sipyco.pc_rpc", "sipyco.sync_struct",
                 "sipyco.asyncio_tools", "sipyco.logging_tools",
                 "sipyco.broadcast", "sipyco.packed_exceptions"]

setup.py

@@ -15,7 +15,7 @@ requirements = [
     "numpy", "scipy",
     "python-dateutil", "prettytable", "h5py",
     "qasync", "pyqtgraph", "pygit2",
-    "llvmlite_artiq", "pythonparser", "python-Levenshtein",
+    "llvmlite", "pythonparser", "python-Levenshtein",
 ]
 
 console_scripts = [