srenblad
/
artiq
forked from M-Labs/artiq
1
0
Fork 0
Code Pull Requests Activity

kasli: fix DRTIO master clock constraint

This commit is contained in:
Sebastien Bourdeauducq 2018-03-29 10:20:31 +08:00
parent 3d89ba2e11
commit 4229c045f4
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
artiq/gateware/targets/kasli.py
View File

@ -684,7 +684,7 @@ class _MasterBase(MiniSoC, AMPSoC):
self.crg.cd_sys.clk,
gtp.txoutclk, gtp.rxoutclk)
for gtp in self.drtio_transceiver.gtps[1:]:
platform.add_period_constraint(gtp.txoutclk, rtio_clk_period)
platform.add_period_constraint(gtp.rxoutclk, rtio_clk_period)
platform.add_false_path_constraints(
self.crg.cd_sys.clk, gtp.rxoutclk)