From 4229c045f4907436e21f1146450f033ac6010ac7 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Thu, 29 Mar 2018 10:20:31 +0800 Subject: [PATCH] kasli: fix DRTIO master clock constraint --- artiq/gateware/targets/kasli.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/artiq/gateware/targets/kasli.py b/artiq/gateware/targets/kasli.py index 22b6a3fbf..c35dabce7 100755 --- a/artiq/gateware/targets/kasli.py +++ b/artiq/gateware/targets/kasli.py @@ -684,7 +684,7 @@ class _MasterBase(MiniSoC, AMPSoC): self.crg.cd_sys.clk, gtp.txoutclk, gtp.rxoutclk) for gtp in self.drtio_transceiver.gtps[1:]: - platform.add_period_constraint(gtp.txoutclk, rtio_clk_period) + platform.add_period_constraint(gtp.rxoutclk, rtio_clk_period) platform.add_false_path_constraints( self.crg.cd_sys.clk, gtp.rxoutclk)