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cri: fix firmware routing table access

This commit is contained in:
Sebastien Bourdeauducq 2018-09-12 18:08:16 +08:00
parent e36a8536d7
commit 420e1cb1d0
4 changed files with 27 additions and 17 deletions

View File

@ -75,8 +75,8 @@ pub fn program_interconnect(rt: &RoutingTable, rank: u8)
for i in 0..DEST_COUNT { for i in 0..DEST_COUNT {
let hop = rt.0[i][rank as usize]; let hop = rt.0[i][rank as usize];
unsafe { unsafe {
csr::cri_con::routing_destination_write(i as _); csr::routing_table::destination_write(i as _);
csr::cri_con::routing_hop_write(hop); csr::routing_table::hop_write(hop);
} }
} }
} }

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@ -1,5 +1,5 @@
from artiq.gateware.rtio.tsc import TSC from artiq.gateware.rtio.tsc import TSC
from artiq.gateware.rtio.cri import KernelInitiator, CRIInterconnectShared from artiq.gateware.rtio.cri import KernelInitiator, CRIInterconnectShared, RoutingTableAccess
from artiq.gateware.rtio.channel import Channel, LogChannel from artiq.gateware.rtio.channel import Channel, LogChannel
from artiq.gateware.rtio.core import Core from artiq.gateware.rtio.core import Core
from artiq.gateware.rtio.analyzer import Analyzer from artiq.gateware.rtio.analyzer import Analyzer

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@ -119,28 +119,15 @@ class CRIDecoder(Module, AutoCSR):
self.slaves = slaves self.slaves = slaves
self.master = master self.master = master
slave_bits = bits_for(len(slaves)-1)
if enable_routing:
self.routing_destination = CSRStorage(8)
self.routing_hop = CSR(slave_bits)
# # # # # #
# routing # routing
slave_bits = bits_for(len(slaves)-1)
selected = Signal(slave_bits) selected = Signal(slave_bits)
if enable_routing: if enable_routing:
self.specials.routing_table = Memory(slave_bits, 256) self.specials.routing_table = Memory(slave_bits, 256)
rtp_csr = self.routing_table.get_port(write_capable=True)
self.specials += rtp_csr
self.comb += [
rtp_csr.adr.eq(self.routing_destination.storage),
rtp_csr.dat_w.eq(self.routing_hop.r),
rtp_csr.we.eq(self.routing_hop.re),
self.routing_hop.w.eq(rtp_csr.dat_r)
]
if mode == "async": if mode == "async":
rtp_decoder = self.routing_table.get_port() rtp_decoder = self.routing_table.get_port()
elif mode == "sync": elif mode == "sync":
@ -220,3 +207,22 @@ class CRIInterconnectShared(Module):
def get_csrs(self): def get_csrs(self):
return self.switch.get_csrs() + self.decoder.get_csrs() return self.switch.get_csrs() + self.decoder.get_csrs()
class RoutingTableAccess(Module, AutoCSR):
def __init__(self, interconnect):
if isinstance(interconnect, CRIInterconnectShared):
interconnect = interconnect.decoder
rtp_csr = interconnect.routing_table.get_port(write_capable=True)
self.specials += rtp_csr
self.destination = CSRStorage(8)
self.hop = CSR(len(rtp_csr.dat_w))
self.comb += [
rtp_csr.adr.eq(self.destination.storage),
rtp_csr.dat_w.eq(self.hop.r),
rtp_csr.we.eq(self.hop.re),
self.hop.w.eq(rtp_csr.dat_r)
]

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@ -730,6 +730,8 @@ class _MasterBase(MiniSoC, AMPSoC):
[self.rtio_core.cri] + self.drtio_cri, [self.rtio_core.cri] + self.drtio_cri,
enable_routing=True) enable_routing=True)
self.register_kernel_cpu_csrdevice("cri_con") self.register_kernel_cpu_csrdevice("cri_con")
self.submodules.routing_table = rtio.RoutingTableAccess(self.cri_con)
self.csr_devices.append("routing_table")
self.submodules.rtio_analyzer = rtio.Analyzer(self.rtio_tsc, self.cri_con.switch.slave, self.submodules.rtio_analyzer = rtio.Analyzer(self.rtio_tsc, self.cri_con.switch.slave,
self.get_native_sdram_if()) self.get_native_sdram_if())
@ -900,6 +902,8 @@ class _SatelliteBase(BaseSoC):
[self.local_io.cri] + self.drtio_cri, [self.local_io.cri] + self.drtio_cri,
mode="sync", enable_routing=True) mode="sync", enable_routing=True)
self.csr_devices.append("cri_con") self.csr_devices.append("cri_con")
self.submodules.routing_table = rtio.RoutingTableAccess(self.cri_con)
self.csr_devices.append("routing_table")
class Master(_MasterBase): class Master(_MasterBase):