From 3fbcf5f303e01ee0903fad0307aa637dc3494f57 Mon Sep 17 00:00:00 2001
From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Fri, 9 Mar 2018 10:36:17 +0800
Subject: [PATCH] drtio: remove TSC correction (#40)

---
 artiq/gateware/drtio/rt_controller_master.py | 9 ++-------
 artiq/gateware/test/drtio/test_full_stack.py | 9 +++------
 2 files changed, 5 insertions(+), 13 deletions(-)

diff --git a/artiq/gateware/drtio/rt_controller_master.py b/artiq/gateware/drtio/rt_controller_master.py
index 24387bda2..786e2aa97 100644
--- a/artiq/gateware/drtio/rt_controller_master.py
+++ b/artiq/gateware/drtio/rt_controller_master.py
@@ -17,7 +17,6 @@ class _CSRs(AutoCSR):
 
         self.protocol_error = CSR(3)
 
-        self.tsc_correction = CSRStorage(64)
         self.set_time = CSR()
         self.underflow_margin = CSRStorage(16, reset=300)
 
@@ -83,13 +82,9 @@ class RTController(Module):
 
         # master RTIO counter and counter synchronization
         self.submodules.counter = RTIOCounter(64-fine_ts_width)
-        self.comb += self.cri.counter.eq(self.counter.value_sys << fine_ts_width)
-        tsc_correction = Signal(64)
-        self.csrs.tsc_correction.storage.attr.add("no_retiming")
-        self.specials += MultiReg(self.csrs.tsc_correction.storage, tsc_correction)
         self.comb += [
-            rt_packet.tsc_value.eq(
-                self.counter.value_rtio + tsc_correction),
+            self.cri.counter.eq(self.counter.value_sys << fine_ts_width),
+            rt_packet.tsc_value.eq(self.counter.value_rtio),
             self.csrs.set_time.w.eq(rt_packet.set_time_stb)
         ]
         self.sync += [
diff --git a/artiq/gateware/test/drtio/test_full_stack.py b/artiq/gateware/test/drtio/test_full_stack.py
index 45d6a4441..82b0d1c79 100644
--- a/artiq/gateware/test/drtio/test_full_stack.py
+++ b/artiq/gateware/test/drtio/test_full_stack.py
@@ -211,7 +211,7 @@ class TestFullStack(unittest.TestCase):
             {"sys": test(), "rtio": tb.check_ttls(ttl_changes)}, self.clocks)
         self.assertEqual(ttl_changes, correct_ttl_changes)
 
-    def test_tsc_error(self):
+    def test_write_underflow(self):
         tb = OutputsTestbench()
 
         def test():
@@ -220,11 +220,8 @@ class TestFullStack(unittest.TestCase):
             yield from tb.init()
             errors = yield from saterr.protocol_error.read()
             self.assertEqual(errors, 0)
-            yield from csrs.tsc_correction.write(100000000)
-            yield from csrs.set_time.write(1)
-            for i in range(15):
-               yield
-            tb.delay(10000)
+            yield from csrs.underflow_margin.write(0)
+            tb.delay(100)
             yield from tb.write(0, 1)
             for i in range(12):
                yield