forked from M-Labs/artiq
gateware.spi: refactor, sim verified
This commit is contained in:
parent
bd9ceb4e12
commit
3b6999ac06
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@ -1,11 +1,158 @@
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from itertools import product
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from migen import *
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from migen.genlib.fsm import *
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from migen.genlib.misc import WaitTimer
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from migen.genlib.fsm import FSM, NextState
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from misoc.interconnect import wishbone
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class SPIClockGen(Module):
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def __init__(self, width):
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self.load = Signal(width)
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self.bias = Signal() # bias this clock phase to longer times
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self.edge = Signal()
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self.clk = Signal(reset=1)
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cnt = Signal.like(self.load)
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self.comb += [
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self.edge.eq(cnt == 0),
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]
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self.sync += [
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cnt.eq(cnt - 1),
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If(self.edge,
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cnt.eq(self.load[1:] +
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(self.load[0] & self.bias)),
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self.clk.eq(~self.clk),
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)
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]
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class SPIRegister(Module):
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def __init__(self, width):
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self.data = Signal(width)
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self.o = Signal()
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self.i = Signal()
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self.lsb = Signal()
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self.shift = Signal()
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self.sample = Signal()
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self.comb += [
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self.o.eq(Mux(self.lsb, self.data[0], self.data[-1])),
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]
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self.sync += [
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If(self.shift,
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If(self.lsb,
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self.data[:-1].eq(self.data[1:]),
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).Else(
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self.data[1:].eq(self.data[:-1]),
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)
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),
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If(self.sample,
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If(self.lsb,
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self.data[-1].eq(self.i),
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).Else(
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self.data[0].eq(self.i),
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)
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)
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]
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class SPIBitCounter(Module):
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def __init__(self, width):
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self.n_read = Signal(width)
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self.n_write = Signal(width)
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self.read = Signal()
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self.write = Signal()
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self.done = Signal()
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self.comb += [
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self.write.eq(self.n_write != 0),
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self.read.eq(self.n_read != 0),
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self.done.eq(~(self.write | self.read)),
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]
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self.sync += [
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If(self.write,
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self.n_write.eq(self.n_write - 1),
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).Elif(self.read,
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self.n_read.eq(self.n_read - 1),
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)
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]
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class SPIMachine(Module):
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def __init__(self, data_width, clock_width, bits_width):
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ce = CEInserter()
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self.submodules.cg = ce(SPIClockGen(clock_width))
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self.submodules.reg = ce(SPIRegister(data_width))
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self.submodules.bits = ce(SPIBitCounter(bits_width))
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self.div_write = Signal.like(self.cg.load)
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self.div_read = Signal.like(self.cg.load)
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self.clk_phase = Signal()
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self.start = Signal()
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self.cs = Signal()
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self.oe = Signal()
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self.done = Signal()
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# # #
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fsm = CEInserter()(FSM("IDLE"))
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self.submodules += fsm
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fsm.act("IDLE",
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If(self.start,
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If(self.clk_phase,
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NextState("WAIT"),
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).Else(
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NextState("SETUP"),
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)
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)
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)
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fsm.act("SETUP",
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self.reg.sample.eq(1),
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NextState("HOLD"),
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)
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fsm.act("HOLD",
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If(self.bits.done & ~self.start,
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If(self.clk_phase,
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NextState("IDLE"),
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).Else(
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NextState("WAIT"),
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)
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).Else(
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self.reg.shift.eq(1),
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NextState("SETUP"),
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)
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)
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fsm.act("WAIT",
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If(self.bits.done,
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NextState("IDLE"),
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).Else(
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NextState("SETUP"),
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)
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)
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write0 = Signal()
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self.sync += [
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If(self.cg.edge & self.reg.shift,
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write0.eq(self.bits.write),
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)
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]
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self.comb += [
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self.cg.ce.eq(self.start | self.cs | ~self.cg.edge),
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If(self.bits.write | ~self.bits.read,
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self.cg.load.eq(self.div_write),
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).Else(
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self.cg.load.eq(self.div_read),
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),
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self.cg.bias.eq(fsm.before_entering("SETUP")),
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fsm.ce.eq(self.cg.edge),
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self.cs.eq(~fsm.ongoing("IDLE")),
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self.reg.ce.eq(self.cg.edge),
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self.bits.ce.eq(self.cg.edge & self.reg.sample),
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self.done.eq(self.cg.edge & self.bits.done & fsm.ongoing("HOLD")),
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self.oe.eq(write0 | self.bits.write),
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]
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class SPIMaster(Module):
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"""SPI Master.
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@ -15,50 +162,61 @@ class SPIMaster(Module):
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* If there is a miso wire in pads, the input and output can be done
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with two signals (a.k.a. 4-wire SPI), else mosi must be used for
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both output and input (a.k.a. 3-wire SPI) and config.half_duplex
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needs to be set.
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* Every transfer consists of a 0-M bit write followed by a 0-M
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bit read.
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* cs_n is always asserted at the beginning and deasserted
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at the end of the transfer.
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must to be set when reading data is desired.
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* Every transfer consists of a write_length 0-M bit write followed
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by a read_length 0-M bit read.
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* cs_n is asserted at the beginning and deasserted at the end of the
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transfer if there is no other transfer pending.
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* cs_n handling is agnostic to whether it is one-hot or decoded
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somewhere downstream. If it is decoded, "cs_n all deasserted"
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should be handled accordingly (no slave selected).
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If it is one-hot, asserting multiple slaves should only be attempted
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if miso is either not connected between slaves or open collector.
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cs can also be handled independently through other means.
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if miso is either not connected between slaves, or open collector,
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or correctly multiplexed externally.
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* If config.cs_polarity == 0 (cs active low, the default),
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"cs_n all deasserted" means "all cs_n bits high".
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* cs is not mandatory in pads. Framing and chip selection can also
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be handled independently through other means.
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* The first bit output on mosi is always the MSB/LSB (depending on
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config.lsb_first) of the data register, independent of
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xfer.write_len. The last bit input from miso always ends up in
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the LSB/MSB (respectively) of the data register, independent of
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read_len.
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* For 4-wire SPI only the sum of read_len and write_len matters. The
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behavior is the same no matter how the transfer length is divided
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between the two. For 3-wire SPI, the direction of mosi/miso is
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switched from output to input after write_len cycles, at the
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"output" clk edge corresponding to bit write_len + 1 of the transfer.
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behavior is the same no matter how the total transfer length is
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divided between the two. For 3-wire SPI, the direction of mosi/miso
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is switched from output to input after write_len cycles, at the
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"shift_out" clk edge corresponding to bit write_length + 1 of the
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transfer.
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* Data output on mosi in 4-wire SPI during the read cycles is what
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is found in the data register at the time.
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Data in the data register outside the least/most (depending
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on config.lsb_first) significant read_len bits is what is
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on config.lsb_first) significant read_length bits is what is
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seen on miso during the write cycles.
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* When the transfer is complete the wishbone transaction is ack-ed.
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* Input data from the last transaction can be read from the data
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register at any time.
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* The SPI data register is double-buffered: once a transfer completes,
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the previous transfer's read data is available in the data register
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and new write data can be written, queuing a new transfer. Transfers
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submitted this way are chained and executed without deasserting cs.
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* A wishbone transaction is ack-ed when the transfer has been written
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to the intermediate buffer. It will be started when there are no
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other transactions being executed.
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Transaction Sequence:
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* If desired, write the config register to set up the core.
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* If desired, write the xfer register to change lengths and cs_n.
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* Write the data register (also for zero-length writes),
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writing triggers the transfer and when the transfer is complete the
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write is ack-ed.
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writing triggers the transfer and when the transfer is accepted to
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the inermediate buffer, the write is ack-ed.
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* If desired, read the data register.
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* If desired write xfer and data for the next, chained, transfer
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Register address and bit map:
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config (address 2):
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1 offline: all pins high-z (reset=1)
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1 active: cs/transfer active
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1 pending: transfer pending in intermediate buffer, bus writes will
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block
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1 cs_polarity: active level of chip select (reset=0)
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1 clk_polarity: idle level for clk (reset=0)
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1 clk_phase: first edge after cs assertion to sample data on (reset=0)
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@ -68,11 +226,11 @@ class SPIMaster(Module):
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(1, 1): idle high, output on falling, input on rising
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1 lsb_first: LSB is the first bit on the wire (reset=0)
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1 half_duplex: 3-wire SPI, in/out on mosi (reset=0)
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10 undefined
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16 clk_load: clock load value to divide from this module's clock
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to the SPI write clk clk pulses are asymmetric
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if a divider is odd, favoring longer setup over hold times.
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clk/spi_clk == clk_load + 2 (reset=0)
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12 div_write: counter load value to divide this module's clock
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to the SPI write clk. clk pulses are asymmetric
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if the value is odd, favoring longer setup over hold times.
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f_clk/f_spi_write == div_write + 2 (reset=0)
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12 div_read: ditto for the read clock
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xfer (address 1):
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16 cs: active high bit mask of chip selects to assert
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@ -89,50 +247,18 @@ class SPIMaster(Module):
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###
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# State machine
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wb_we = Signal()
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start = Signal()
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active = Signal()
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fsm = FSM("IDLE")
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self.submodules += fsm
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fsm.act("IDLE",
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If(bus.cyc & bus.stb,
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NextState("ACK"),
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If(bus.we,
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wb_we.eq(1),
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If(bus.adr == 0, # data register
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NextState("START"),
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)
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)
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)
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)
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fsm.act("START",
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start.eq(1),
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NextState("ACTIVE"),
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)
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fsm.act("ACTIVE",
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If(~active,
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bus.ack.eq(1),
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NextState("IDLE"),
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)
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)
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fsm.act("ACK",
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bus.ack.eq(1),
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NextState("IDLE"),
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)
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# Wishbone
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config = Record([
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("offline", 1),
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("active", 1),
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("pending", 1),
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("cs_polarity", 1),
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("clk_polarity", 1),
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("clk_phase", 1),
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("lsb_first", 1),
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("half_duplex", 1),
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("padding", 10),
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("clk_load", 16),
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("div_write", 12),
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("div_read", 12),
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])
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config.offline.reset = 1
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assert len(config) <= len(bus.dat_w)
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@ -144,101 +270,96 @@ class SPIMaster(Module):
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])
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assert len(xfer) <= len(bus.dat_w)
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data = Signal.like(bus.dat_w)
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wb_data = Array([data, xfer.raw_bits(), config.raw_bits()])[bus.adr]
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self.comb += bus.dat_r.eq(wb_data)
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self.sync += If(wb_we, wb_data.eq(bus.dat_w))
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# SPI
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write_count = Signal.like(xfer.write_length)
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read_count = Signal.like(xfer.read_length)
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clk_count = Signal.like(config.clk_load)
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clk = Signal(reset=1) # idle high
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phase = Signal()
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edge = Signal()
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write = Signal()
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read = Signal()
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miso = Signal()
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miso_i = Signal()
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mosi_o = Signal()
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spi = SPIMachine(data_width, clock_width=len(config.div_read),
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bits_width=len(xfer.read_length))
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self.submodules += spi
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wb_we = Signal()
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pending = Signal()
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cs = Signal.like(xfer.cs)
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data_read = Signal.like(spi.reg.data)
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data_write = Signal.like(spi.reg.data)
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self.comb += [
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phase.eq(clk ^ config.clk_phase),
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edge.eq(active & (clk_count == 0)),
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write.eq(write_count != 0),
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read.eq(read_count != 0),
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wb_we.eq(bus.cyc & bus.stb & bus.we & (~pending | spi.done)),
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bus.dat_r.eq(
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Array([data_read, xfer.raw_bits(), config.raw_bits()
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])[bus.adr]),
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spi.start.eq(pending & (~spi.cs | spi.done)),
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spi.clk_phase.eq(config.clk_phase),
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spi.reg.lsb.eq(config.lsb_first),
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spi.div_write.eq(config.div_write),
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spi.div_read.eq(config.div_read),
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]
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self.sync += [
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If(start,
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write_count.eq(xfer.write_length),
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read_count.eq(xfer.read_length),
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active.eq(1),
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bus.ack.eq(~bus.we | ~pending | spi.done),
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If(wb_we,
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Array([data_write, xfer.raw_bits(), config.raw_bits()
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])[bus.adr].eq(bus.dat_w)
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),
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If(active,
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clk_count.eq(clk_count - 1),
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config.active.eq(spi.cs),
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config.pending.eq(pending),
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If(spi.done,
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data_read.eq(spi.reg.data),
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),
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If(start | edge,
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# setup time passes during phase 0
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# use the lsb to bias that time to favor longer setup times
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clk_count.eq(config.clk_load[1:] +
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(config.clk_load[0] & phase)),
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clk.eq(~clk), # idle high
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If(phase,
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data.eq(Mux(config.lsb_first,
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Cat(data[1:], miso),
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Cat(miso, data[:-1]))),
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mosi_o.eq(Mux(config.lsb_first, data[0], data[-1])),
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If(write,
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write_count.eq(write_count - 1),
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If(spi.start,
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cs.eq(xfer.cs),
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spi.bits.n_write.eq(xfer.write_length),
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spi.bits.n_read.eq(xfer.read_length),
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spi.reg.data.eq(data_write),
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pending.eq(0),
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),
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).Else(
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miso.eq(miso_i),
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If(~write & read,
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read_count.eq(read_count - 1),
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),
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),
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),
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If(~clk & edge & ~write & ~read, # always from low clk
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active.eq(0),
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If(wb_we & (bus.adr == 0), # data register
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pending.eq(1),
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),
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]
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# I/O
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if hasattr(pads, "cs_n"):
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cs_n_t = TSTriple(len(pads.cs_n))
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self.specials += cs_n_t.get_tristate(pads.cs_n)
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self.comb += [
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cs_n_t.oe.eq(~config.offline),
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cs_n_t.o.eq((cs & Replicate(spi.cs, len(cs))) ^
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Replicate(~config.cs_polarity, len(cs))),
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]
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clk_t = TSTriple()
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self.specials += clk_t.get_tristate(pads.clk)
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mosi_t = TSTriple()
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self.specials += mosi_t.get_tristate(pads.mosi)
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self.comb += [
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cs_n_t.oe.eq(~config.offline),
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clk_t.oe.eq(~config.offline),
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mosi_t.oe.eq(~config.offline & (write | ~config.half_duplex)),
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cs_n_t.o.eq((xfer.cs & Replicate(active, len(xfer.cs))) ^
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Replicate(~config.cs_polarity, len(xfer.cs))),
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clk_t.o.eq((clk & active) ^ config.clk_polarity),
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miso_i.eq(Mux(config.half_duplex, mosi_t.i,
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mosi_t.oe.eq(~config.offline & spi.cs &
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(spi.oe | ~config.half_duplex)),
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clk_t.o.eq((spi.cg.clk & spi.cs) ^ config.clk_polarity),
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spi.reg.i.eq(Mux(config.half_duplex, mosi_t.i,
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getattr(pads, "miso", mosi_t.i))),
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mosi_t.o.eq(mosi_o),
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mosi_t.o.eq(spi.reg.o),
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]
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SPI_CONFIG_ADDR = 2
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SPI_XFER_ADDR = 1
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SPI_DATA_ADDR = 0
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SPI_OFFLINE = 1 << 0
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SPI_CS_POLARITY = 1 << 1
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SPI_CLK_POLARITY = 1 << 2
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SPI_CLK_PHASE = 1 << 3
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SPI_LSB_FIRST = 1 << 4
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SPI_HALF_DUPLEX = 1 << 5
|
||||
SPI_DATA_ADDR, SPI_XFER_ADDR, SPI_CONFIG_ADDR = range(3)
|
||||
(
|
||||
SPI_OFFLINE,
|
||||
SPI_ACTIVE,
|
||||
SPI_PENDING,
|
||||
SPI_CS_POLARITY,
|
||||
SPI_CLK_POLARITY,
|
||||
SPI_CLK_PHASE,
|
||||
SPI_LSB_FIRST,
|
||||
SPI_HALF_DUPLEX,
|
||||
) = (1 << i for i in range(8))
|
||||
|
||||
|
||||
def SPI_CLK_LOAD(i):
|
||||
return i << 16
|
||||
def SPI_DIV_WRITE(i):
|
||||
return i << 8
|
||||
|
||||
|
||||
def SPI_DIV_READ(i):
|
||||
return i << 20
|
||||
|
||||
|
||||
def SPI_CS(i):
|
||||
|
|
@ -253,53 +374,44 @@ def SPI_READ_LENGTH(i):
|
|||
return i << 24
|
||||
|
||||
|
||||
def _test_gen(bus):
|
||||
yield from bus.write(SPI_CONFIG_ADDR,
|
||||
1*SPI_CLK_PHASE | 0*SPI_LSB_FIRST |
|
||||
1*SPI_HALF_DUPLEX | SPI_CLK_LOAD(3))
|
||||
yield
|
||||
yield from bus.write(SPI_XFER_ADDR, SPI_CS(0b00001) |
|
||||
SPI_WRITE_LENGTH(4) | SPI_READ_LENGTH(0))
|
||||
yield
|
||||
yield from bus.write(SPI_DATA_ADDR, 0x90000000)
|
||||
yield
|
||||
print(hex((yield from bus.read(SPI_DATA_ADDR))))
|
||||
yield
|
||||
yield from bus.write(SPI_XFER_ADDR, SPI_CS(0b00010) |
|
||||
SPI_WRITE_LENGTH(4) | SPI_READ_LENGTH(4))
|
||||
yield
|
||||
yield from bus.write(SPI_DATA_ADDR, 0x81000000)
|
||||
yield
|
||||
print(hex((yield from bus.read(SPI_DATA_ADDR))))
|
||||
yield
|
||||
yield from bus.write(SPI_XFER_ADDR, SPI_CS(0b00010) |
|
||||
SPI_WRITE_LENGTH(0) | SPI_READ_LENGTH(4))
|
||||
yield
|
||||
yield from bus.write(SPI_DATA_ADDR, 0x90000000)
|
||||
yield
|
||||
print(hex((yield from bus.read(SPI_DATA_ADDR))))
|
||||
yield
|
||||
yield from bus.write(SPI_XFER_ADDR, SPI_CS(0b00010) |
|
||||
SPI_WRITE_LENGTH(32) | SPI_READ_LENGTH(0))
|
||||
yield
|
||||
yield from bus.write(SPI_DATA_ADDR, 0x87654321)
|
||||
yield
|
||||
print(hex((yield from bus.read(SPI_DATA_ADDR))))
|
||||
def _test_xfer(bus, cs, wlen, rlen, wdata):
|
||||
yield from bus.write(SPI_XFER_ADDR, SPI_CS(cs) |
|
||||
SPI_WRITE_LENGTH(wlen) | SPI_READ_LENGTH(rlen))
|
||||
yield from bus.write(SPI_DATA_ADDR, wdata)
|
||||
yield
|
||||
|
||||
|
||||
def _test_read(bus, sync=SPI_ACTIVE | SPI_PENDING):
|
||||
while (yield from bus.read(SPI_CONFIG_ADDR)) & sync:
|
||||
pass
|
||||
return (yield from bus.read(SPI_DATA_ADDR))
|
||||
|
||||
|
||||
def _test_gen(bus):
|
||||
yield from bus.write(SPI_CONFIG_ADDR,
|
||||
0*SPI_CLK_PHASE | 0*SPI_LSB_FIRST |
|
||||
1*SPI_HALF_DUPLEX |
|
||||
SPI_DIV_WRITE(3) | SPI_DIV_READ(5))
|
||||
yield from _test_xfer(bus, 0b01, 4, 0, 0x90000000)
|
||||
print(hex((yield from _test_read(bus))))
|
||||
yield from _test_xfer(bus, 0b10, 0, 4, 0x90000000)
|
||||
print(hex((yield from _test_read(bus))))
|
||||
yield from _test_xfer(bus, 0b11, 4, 4, 0x81000000)
|
||||
print(hex((yield from _test_read(bus))))
|
||||
yield from _test_xfer(bus, 0b01, 8, 32, 0x87654321)
|
||||
yield from _test_xfer(bus, 0b01, 0, 32, 0x12345678)
|
||||
print(hex((yield from _test_read(bus, SPI_PENDING))))
|
||||
print(hex((yield from _test_read(bus, SPI_ACTIVE))))
|
||||
return
|
||||
for cpol, cpha, lsb, clk in product(
|
||||
(0, 1), (0, 1), (0, 1), (0, 1)):
|
||||
yield from bus.write(SPI_CONFIG_ADDR,
|
||||
cpol*SPI_CLK_POLARITY | cpha*SPI_CLK_PHASE |
|
||||
lsb*SPI_LSB_FIRST | SPI_CLK_LOAD(clk))
|
||||
lsb*SPI_LSB_FIRST | SPI_DIV_WRITE(clk) |
|
||||
SPI_DIV_READ(clk))
|
||||
for wlen, rlen, wdata in product((0, 8, 32), (0, 8, 32),
|
||||
(0, 0xffffffff, 0xdeadbeef)):
|
||||
yield from bus.write(SPI_XFER_ADDR, SPI_CS(0b00001) |
|
||||
SPI_WRITE_LENGTH(wlen) |
|
||||
SPI_READ_LENGTH(rlen))
|
||||
yield from bus.write(SPI_DATA_ADDR, wdata)
|
||||
rdata = yield from bus.read(SPI_DATA_ADDR)
|
||||
rdata = (yield from _test_xfer(bus, 0b1, wlen, rlen, wdata, True))
|
||||
len = (wlen + rlen) % 32
|
||||
mask = (1 << len) - 1
|
||||
if lsb:
|
||||
|
|
@ -336,10 +448,10 @@ if __name__ == "__main__":
|
|||
]
|
||||
Tristate.lower = staticmethod(lambda dr: T(dr))
|
||||
|
||||
from migen.fhdl.verilog import convert
|
||||
pads = _TestPads()
|
||||
dut = SPIMaster(pads)
|
||||
dut.comb += pads.miso.eq(pads.mosi)
|
||||
# from migen.fhdl.verilog import convert
|
||||
# print(convert(dut))
|
||||
|
||||
run_simulation(dut, _test_gen(dut.bus), vcd_name="spi_master.vcd")
|
||||
|
|
|
|||
Loading…
Reference in New Issue