forked from M-Labs/artiq
gateware.spi: add complete spi master logic
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@ -1,3 +1,5 @@
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from itertools import product
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from migen import *
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from migen.genlib.fsm import *
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from migen.genlib.misc import WaitTimer
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@ -8,18 +10,22 @@ class SPIMaster(Module):
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"""SPI Master.
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Notes:
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* If there is a miso wire in pads, the input and output are done with
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two signals (a.k.a. 4-wire SPI), else mosi is used for both output
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and input (a.k.a. 3-wire SPI).
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* Every transfer consists of a 0-32 bit write followed by a 0-32
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* M = 32 is the data width (width of the data register,
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maximum write bits, maximum read bits)
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* If there is a miso wire in pads, the input and output can be done
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with two signals (a.k.a. 4-wire SPI), else mosi must be used for
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both output and input (a.k.a. 3-wire SPI) and config.half_duplex
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needs to be set.
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* Every transfer consists of a 0-M bit write followed by a 0-M
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bit read.
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* cs_n is always asserted at the beginning and deasserted
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at the end of the tranfer.
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at the end of the transfer.
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* cs_n handling is agnostic to whether it is one-hot or decoded
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somewhere downstream. If it is decoded, "cs_n all deasserted"
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should be handled accordingly (no slave selected).
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If it is one-hot, asserting multiple slaves should only be attempted
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if miso is either not connected between slaves or open collector.
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cs can also be handled independently through other means.
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* If config.cs_polarity == 0 (cs active low, the default),
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"cs_n all deasserted" means "all cs_n bits high".
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* The first bit output on mosi is always the MSB/LSB (depending on
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@ -32,24 +38,26 @@ class SPIMaster(Module):
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between the two. For 3-wire SPI, the direction of mosi/miso is
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switched from output to input after write_len cycles, at the
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"output" clk edge corresponding to bit write_len + 1 of the transfer.
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* Data output on mosi in 4-wire SPI during the read cycles is
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undefined. Data in the data register outside the
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least/most (depending on config.lsb_first) significant read_len
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bits is undefined.
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* The transfer is complete when the wishbone transaction is ack-ed.
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* Data output on mosi in 4-wire SPI during the read cycles is what
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is found in the data register at the time.
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Data in the data register outside the least/most (depending
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on config.lsb_first) significant read_len bits is what is
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seen on miso during the write cycles.
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* When the transfer is complete the wishbone transaction is ack-ed.
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* Input data from the last transaction can be read from the data
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register at any time.
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Transaction Sequence:
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* if desired, write the xfer register to change lengths and cs_n.
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* write the data register (also for zero-length writes),
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writing triggers the transfer and the transfer is complete when the
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write is complete.
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* if desired, read the data register
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* If desired, write the config register to set up the core.
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* If desired, write the xfer register to change lengths and cs_n.
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* Write the data register (also for zero-length writes),
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writing triggers the transfer and when the transfer is complete the
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write is ack-ed.
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* If desired, read the data register.
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Register address and bit map:
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config (address 0):
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config (address 2):
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1 offline: all pins high-z (reset=1)
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1 cs_polarity: active level of chip select (reset=0)
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1 clk_polarity: idle level for clk (reset=0)
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@ -59,40 +67,252 @@ class SPIMaster(Module):
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(1, 0): idle high, output on rising, input on falling
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(1, 1): idle high, output on falling, input on rising
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1 lsb_first: LSB is the first bit on the wire (reset=0)
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11 undefined
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16 speed: divider from this module's clock to the SPI clk
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(minimum=2, reset=4)
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clk pulses are asymmetric if speed is odd, favoring longer setup
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over hold times
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1 half_duplex: 3-wire SPI, in/out on mosi (reset=0)
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10 undefined
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16 clk_load: clock load value to divide from this module's clock
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to the SPI write clk clk pulses are asymmetric
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if a divider is odd, favoring longer setup over hold times.
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clk/spi_clk == clk_load + 2 (reset=0)
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xfer (address 1):
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16 cs: active high bit mask of chip selects to assert
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6 write_len: 0-32 bits
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2 undefined
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6 read_len: 0-32 bits
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2 undefined
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8 write_len: 0-M bits
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8 read_len: 0-M bits
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data (address 2):
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32 write/read data
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data (address 0):
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M write/read data
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"""
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def __init__(self, pads, bus=None):
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def __init__(self, pads, bus=None, data_width=32):
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if bus is None:
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bus = wishbone.Interface(data_width=32)
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bus = wishbone.Interface(data_width=data_width)
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self.bus = bus
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###
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# State machine
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wb_we = Signal()
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start = Signal()
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active = Signal()
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fsm = FSM("IDLE")
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self.submodules += fsm
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fsm.act("IDLE",
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If(bus.cyc & bus.stb,
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NextState("ACK"),
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If(bus.we,
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wb_we.eq(1),
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If(bus.adr == 0, # data register
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NextState("START"),
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)
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)
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)
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)
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fsm.act("START",
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start.eq(1),
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NextState("ACTIVE"),
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)
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fsm.act("ACTIVE",
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If(~active,
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bus.ack.eq(1),
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NextState("IDLE"),
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)
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)
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fsm.act("ACK",
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bus.ack.eq(1),
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NextState("IDLE"),
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)
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# Wishbone
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config = Record([
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("offline", 1),
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("cs_polarity", 1),
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("clk_polarity", 1),
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("clk_phase", 1),
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("lsb_first", 1),
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("half_duplex", 1),
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("padding", 10),
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("clk_load", 16),
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])
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config.offline.reset = 1
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assert len(config) <= len(bus.dat_w)
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xfer = Record([
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("cs", 16),
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("write_length", 8),
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("read_length", 8),
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])
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assert len(xfer) <= len(bus.dat_w)
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data = Signal.like(bus.dat_w)
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wb_data = Array([data, xfer.raw_bits(), config.raw_bits()])[bus.adr]
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self.comb += bus.dat_r.eq(wb_data)
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self.sync += If(wb_we, wb_data.eq(bus.dat_w))
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# SPI
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write_count = Signal.like(xfer.write_length)
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read_count = Signal.like(xfer.read_length)
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clk_count = Signal.like(config.clk_load)
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clk = Signal(reset=1) # idle high
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phase = Signal()
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edge = Signal()
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write = Signal()
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read = Signal()
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miso = Signal()
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miso_i = Signal()
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mosi_o = Signal()
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self.comb += [
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phase.eq(clk ^ config.clk_phase),
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edge.eq(active & (clk_count == 0)),
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write.eq(write_count != 0),
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read.eq(read_count != 0),
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]
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self.sync += [
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If(start,
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write_count.eq(xfer.write_length),
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read_count.eq(xfer.read_length),
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active.eq(1),
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),
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If(active,
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clk_count.eq(clk_count - 1),
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),
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If(start | edge,
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# setup time passes during phase 0
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# use the lsb to bias that time to favor longer setup times
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clk_count.eq(config.clk_load[1:] +
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(config.clk_load[0] & phase)),
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clk.eq(~clk), # idle high
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If(phase,
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data.eq(Mux(config.lsb_first,
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Cat(data[1:], miso),
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Cat(miso, data[:-1]))),
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mosi_o.eq(Mux(config.lsb_first, data[0], data[-1])),
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If(write,
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write_count.eq(write_count - 1),
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),
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).Else(
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miso.eq(miso_i),
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If(~write & read,
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read_count.eq(read_count - 1),
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),
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),
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),
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If(~clk & edge & ~write & ~read, # always from low clk
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active.eq(0),
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),
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]
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# I/O
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cs_n_t = TSTriple(len(pads.cs_n))
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self.specials += cs_n_t.get_tristate(pads.cs_n)
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clk_t = TSTriple()
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self.specials += clk_t.get_tristate(pads.clk)
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mosi_t = TSTriple()
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self.specials += mosi_t.get_tristate(pads.mosi)
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self.comb += [
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cs_n_t.oe.eq(~config.offline),
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clk_t.oe.eq(~config.offline),
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mosi_t.oe.eq(~config.offline & (write | ~config.half_duplex)),
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cs_n_t.o.eq((xfer.cs & Replicate(active, len(xfer.cs))) ^
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Replicate(~config.cs_polarity, len(xfer.cs))),
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clk_t.o.eq((clk & active) ^ config.clk_polarity),
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miso_i.eq(Mux(config.half_duplex, mosi_t.i,
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getattr(pads, "miso", mosi_t.i))),
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mosi_t.o.eq(mosi_o),
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]
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SPI_CONFIG_ADDR = 2
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SPI_XFER_ADDR = 1
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SPI_DATA_ADDR = 0
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SPI_OFFLINE = 1 << 0
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SPI_CS_POLARITY = 1 << 1
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SPI_CLK_POLARITY = 1 << 2
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SPI_CLK_PHASE = 1 << 3
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SPI_LSB_FIRST = 1 << 4
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SPI_HALF_DUPLEX = 1 << 5
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def SPI_CLK_LOAD(i):
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return i << 16
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def SPI_CS(i):
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return i << 0
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def SPI_WRITE_LENGTH(i):
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return i << 16
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def SPI_READ_LENGTH(i):
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return i << 24
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def _test_gen(bus):
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yield from bus.write(0, 0 | (5 << 16))
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yield from bus.write(SPI_CONFIG_ADDR,
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1*SPI_CLK_PHASE | 0*SPI_LSB_FIRST |
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1*SPI_HALF_DUPLEX | SPI_CLK_LOAD(3))
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yield
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yield from bus.write(1, 1 | (24 << 16) | (16 << 24))
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yield from bus.write(SPI_XFER_ADDR, SPI_CS(0b00001) |
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SPI_WRITE_LENGTH(4) | SPI_READ_LENGTH(0))
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yield
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yield from bus.write(2, 0x12345678)
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yield from bus.write(SPI_DATA_ADDR, 0x90000000)
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yield
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r = (yield from bus.read(2))
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print(r)
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print(hex((yield from bus.read(SPI_DATA_ADDR))))
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yield
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yield from bus.write(SPI_XFER_ADDR, SPI_CS(0b00010) |
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SPI_WRITE_LENGTH(4) | SPI_READ_LENGTH(4))
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yield
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yield from bus.write(SPI_DATA_ADDR, 0x81000000)
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yield
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print(hex((yield from bus.read(SPI_DATA_ADDR))))
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yield
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yield from bus.write(SPI_XFER_ADDR, SPI_CS(0b00010) |
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SPI_WRITE_LENGTH(0) | SPI_READ_LENGTH(4))
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yield
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yield from bus.write(SPI_DATA_ADDR, 0x90000000)
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yield
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print(hex((yield from bus.read(SPI_DATA_ADDR))))
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yield
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yield from bus.write(SPI_XFER_ADDR, SPI_CS(0b00010) |
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SPI_WRITE_LENGTH(32) | SPI_READ_LENGTH(0))
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yield
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yield from bus.write(SPI_DATA_ADDR, 0x87654321)
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yield
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print(hex((yield from bus.read(SPI_DATA_ADDR))))
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yield
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return
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for cpol, cpha, lsb, clk in product(
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(0, 1), (0, 1), (0, 1), (0, 1)):
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yield from bus.write(SPI_CONFIG_ADDR,
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cpol*SPI_CLK_POLARITY | cpha*SPI_CLK_PHASE |
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lsb*SPI_LSB_FIRST | SPI_CLK_LOAD(clk))
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for wlen, rlen, wdata in product((0, 8, 32), (0, 8, 32),
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(0, 0xffffffff, 0xdeadbeef)):
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yield from bus.write(SPI_XFER_ADDR, SPI_CS(0b00001) |
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SPI_WRITE_LENGTH(wlen) |
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SPI_READ_LENGTH(rlen))
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yield from bus.write(SPI_DATA_ADDR, wdata)
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rdata = yield from bus.read(SPI_DATA_ADDR)
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len = (wlen + rlen) % 32
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mask = (1 << len) - 1
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if lsb:
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shift = (wlen + rlen) % 32
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else:
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shift = 0
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a = (wdata >> wshift) & wmask
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b = (rdata >> rshift) & rmask
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if a != b:
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print("ERROR", end=" ")
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print(cpol, cpha, lsb, clk, wlen, rlen,
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hex(wdata), hex(rdata), hex(a), hex(b))
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class _TestPads:
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@ -104,6 +324,22 @@ class _TestPads:
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if __name__ == "__main__":
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from migen.fhdl.specials import Tristate
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class T(Module):
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def __init__(self, t):
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oe = Signal()
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self.comb += [
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t.target.eq(t.o),
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oe.eq(t.oe),
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t.i.eq(t.o),
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]
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Tristate.lower = staticmethod(lambda dr: T(dr))
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from migen.fhdl.verilog import convert
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pads = _TestPads()
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dut = SPIMaster(pads)
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dut.comb += pads.miso.eq(pads.mosi)
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#print(convert(dut))
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run_simulation(dut, _test_gen(dut.bus), vcd_name="spi_master.vcd")
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