forked from M-Labs/artiq
sayma_amc: change test patterns for 'without-sawg'
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@ -122,11 +122,37 @@ class AD9154NoSAWG(Module, AutoCSR):
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self.sawgs = []
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for i, conv in enumerate(self.jesd.core.sink.flatten()):
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ramp = Signal(16)
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self.sync.rtio += ramp.eq(ramp + (1 << 9 + i))
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self.comb += conv.eq(Cat(ramp
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for i in range(len(conv) // len(ramp))))
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ramp = Signal(4)
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self.sync.rtio += ramp.eq(ramp + 1)
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samples = [[Signal(16) for i in range(4)] for j in range(4)]
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self.comb += [
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a.eq(Cat(b)) for a, b in zip(
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self.jesd.core.sink.flatten(), samples)
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]
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# ch0: 16-step ramp with big carry toggles
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for i in range(4):
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self.comb += [
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samples[0][i][-4:].eq(ramp),
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samples[0][i][:-4].eq(0x7ff if i % 2 else 0x800)
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]
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# ch1: 50 MHz
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from math import pi, cos
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data = [int(round(cos(i/12*2*pi)*((1 << 15) - 1)))
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for i in range(12)]
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k = Signal(2)
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self.sync.rtio += If(k == 2, k.eq(0)).Else(k.eq(k + 1))
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self.comb += [
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Case(k, {
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i: [samples[1][j].eq(data[i*4 + j]) for j in range(4)]
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for i in range(3)
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})
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]
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# ch2: ch0, ch3: ch1
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self.comb += [
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Cat(samples[2]).eq(Cat(samples[0])),
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Cat(samples[3]).eq(Cat(samples[1]))
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]
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class Standalone(MiniSoC, AMPSoC):
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