srenblad
/
artiq
forked from M-Labs/artiq
1
0
Fork 0
Code Pull Requests Activity

pipistrello: smaller L2 cache

This commit is contained in:
Sébastien Bourdeauducq 2015-06-18 09:49:52 -06:00
parent 77ca8bbf0f
commit 3636025e69
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
soc/targets/artiq_pipistrello.py
View File

@ -71,7 +71,7 @@ class NIST_QC1(BaseSoC, AMPSoC):
def __init__(self, platform, cpu_type="or1k", **kwargs): def __init__(self, platform, cpu_type="or1k", **kwargs):
BaseSoC.__init__(self, platform, BaseSoC.__init__(self, platform,
cpu_type=cpu_type, cpu_type=cpu_type,
sdram_controller_settings=MiniconSettings(l2_size=128*1024), sdram_controller_settings=MiniconSettings(l2_size=64*1024),
with_timer=False, **kwargs) with_timer=False, **kwargs)
AMPSoC.__init__(self) AMPSoC.__init__(self)
platform.toolchain.ise_commands += """ platform.toolchain.ise_commands += """