From 3636025e69c8c299280a0650be2b2053298136aa Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?S=C3=A9bastien=20Bourdeauducq?= Date: Thu, 18 Jun 2015 09:49:52 -0600 Subject: [PATCH] pipistrello: smaller L2 cache --- soc/targets/artiq_pipistrello.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/soc/targets/artiq_pipistrello.py b/soc/targets/artiq_pipistrello.py index 1b1dd71f9..f18c7cfe0 100644 --- a/soc/targets/artiq_pipistrello.py +++ b/soc/targets/artiq_pipistrello.py @@ -71,7 +71,7 @@ class NIST_QC1(BaseSoC, AMPSoC): def __init__(self, platform, cpu_type="or1k", **kwargs): BaseSoC.__init__(self, platform, cpu_type=cpu_type, - sdram_controller_settings=MiniconSettings(l2_size=128*1024), + sdram_controller_settings=MiniconSettings(l2_size=64*1024), with_timer=False, **kwargs) AMPSoC.__init__(self) platform.toolchain.ise_commands += """