From 354d82cfe3b912d31de163bdd556a250b1e930cd Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Thu, 28 Nov 2019 17:40:00 +0800 Subject: [PATCH] wrpll: drive helper clock domain --- artiq/firmware/libboard_artiq/wrpll.rs | 7 +++++++ artiq/gateware/drtio/wrpll/core.py | 13 ++++++++++++- artiq/gateware/targets/sayma_amc.py | 1 + 3 files changed, 20 insertions(+), 1 deletion(-) diff --git a/artiq/firmware/libboard_artiq/wrpll.rs b/artiq/firmware/libboard_artiq/wrpll.rs index 125b47e69..0a075beff 100644 --- a/artiq/firmware/libboard_artiq/wrpll.rs +++ b/artiq/firmware/libboard_artiq/wrpll.rs @@ -1,3 +1,5 @@ +use board_misoc::{csr, clock}; + mod i2c { use board_misoc::{csr, clock}; @@ -272,6 +274,8 @@ mod si549 { pub fn init() { info!("initializing..."); + unsafe { csr::wrpll::helper_reset_write(1); } + #[cfg(rtio_frequency = "125.0")] let (m_hsdiv, m_lsdiv, m_fbdiv) = (0x017, 2, 0x04b5badb98a); #[cfg(rtio_frequency = "125.0")] @@ -281,6 +285,9 @@ pub fn init() { .expect("cannot initialize main Si549"); si549::program(i2c::Dcxo::Helper, h_hsdiv, h_lsdiv, h_fbdiv) .expect("cannot initialize helper Si549"); + + clock::spin_us(10_000); // Settling Time after FS Change + unsafe { csr::wrpll::helper_reset_write(0); } } pub fn select_recovered_clock(rc: bool) { diff --git a/artiq/gateware/drtio/wrpll/core.py b/artiq/gateware/drtio/wrpll/core.py index 77c11fb3b..4c2a35a91 100644 --- a/artiq/gateware/drtio/wrpll/core.py +++ b/artiq/gateware/drtio/wrpll/core.py @@ -1,10 +1,21 @@ from migen import * +from migen.genlib.resetsync import AsyncResetSynchronizer from misoc.interconnect.csr import * from artiq.gateware.drtio.wrpll.si549 import Si549 class WRPLL(Module, AutoCSR): - def __init__(self, main_dcxo_i2c, helper_dxco_i2c): + def __init__(self, helper_clk_pads, main_dcxo_i2c, helper_dxco_i2c): + self.helper_reset = CSRStorage(reset=1) + + self.clock_domains.cd_helper = ClockDomain() + self.helper_reset.storage.attr.add("no_retiming") + self.specials += [ + Instance("IBUFGDS", i_I=helper_clk_pads.p, i_IB=helper_clk_pads.n, + o_O=self.cd_helper.clk), + AsyncResetSynchronizer(self.cd_helper, self.helper_reset.storage) + ] + self.submodules.main_dcxo = Si549(main_dcxo_i2c) self.submodules.helper_dcxo = Si549(helper_dxco_i2c) diff --git a/artiq/gateware/targets/sayma_amc.py b/artiq/gateware/targets/sayma_amc.py index 4e2341037..8487fdf40 100755 --- a/artiq/gateware/targets/sayma_amc.py +++ b/artiq/gateware/targets/sayma_amc.py @@ -137,6 +137,7 @@ class SatelliteBase(MiniSoC): platform.request("ddmtd_helper_dcxo_oe").eq(1) ] self.submodules.wrpll = WRPLL( + helper_clk_pads=platform.request("ddmtd_helper_clk"), main_dcxo_i2c=platform.request("ddmtd_main_dcxo_i2c"), helper_dxco_i2c=platform.request("ddmtd_helper_dcxo_i2c")) self.csr_devices.append("wrpll")