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dsp/fir: outputs reset_less (pipelined)

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Robert Jördens 2018-03-13 17:11:50 +00:00
parent 2edf65f57b
commit 2fdc180601
1 changed files with 1 additions and 1 deletions
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2
artiq/gateware/dsp/fir.py
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@ -69,7 +69,7 @@ class ParallelFIR(Module):
n = len(coefficients)
# input and output: old to new, decreasing delay
self.i = [Signal((width, True)) for i in range(p)]
self.o = [Signal((width, True)) for i in range(p)]
self.o = [Signal((width, True), reset_less=True) for i in range(p)]
self.latency = (n + 1)//2//p + 2
w = _widths[arch]