From 2fdc18060148f3f372a0c6db756d913a0a0ebd6b Mon Sep 17 00:00:00 2001 From: Robert Jordens Date: Tue, 13 Mar 2018 17:11:50 +0000 Subject: [PATCH] dsp/fir: outputs reset_less (pipelined) --- artiq/gateware/dsp/fir.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/artiq/gateware/dsp/fir.py b/artiq/gateware/dsp/fir.py index 516ca5c7f..002487e32 100644 --- a/artiq/gateware/dsp/fir.py +++ b/artiq/gateware/dsp/fir.py @@ -69,7 +69,7 @@ class ParallelFIR(Module): n = len(coefficients) # input and output: old to new, decreasing delay self.i = [Signal((width, True)) for i in range(p)] - self.o = [Signal((width, True)) for i in range(p)] + self.o = [Signal((width, True), reset_less=True) for i in range(p)] self.latency = (n + 1)//2//p + 2 w = _widths[arch]