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unflip logic..

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SingularitySurfer 2022-06-23 10:20:38 +00:00
parent 3f8a221c76
commit 2e834cf406
1 changed files with 1 additions and 1 deletions
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artiq/coredevice/phaser.py
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@ -1094,7 +1094,7 @@ class PhaserChannel:
raise ValueError("invalid profile index")
addr = PHASER_ADDR_SERVO_CFG0 + self.index
# enforce hold if the servo is bypassed
data = (profile << 2) | (((hold | bypass) & 1) << 1) | (bypass & 1)
data = (profile << 2) | (((hold | bypass) & 1) << 1) | (~bypass & 1)
self.phaser.write8(addr, data)
@kernel