From 2e834cf406426bf844435b653f2dd39775c75c32 Mon Sep 17 00:00:00 2001 From: SingularitySurfer Date: Thu, 23 Jun 2022 10:20:38 +0000 Subject: [PATCH] unflip logic.. --- artiq/coredevice/phaser.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/artiq/coredevice/phaser.py b/artiq/coredevice/phaser.py index 76e9fec7e..bb3cfd6df 100644 --- a/artiq/coredevice/phaser.py +++ b/artiq/coredevice/phaser.py @@ -1094,7 +1094,7 @@ class PhaserChannel: raise ValueError("invalid profile index") addr = PHASER_ADDR_SERVO_CFG0 + self.index # enforce hold if the servo is bypassed - data = (profile << 2) | (((hold | bypass) & 1) << 1) | (bypass & 1) + data = (profile << 2) | (((hold | bypass) & 1) << 1) | (~bypass & 1) self.phaser.write8(addr, data) @kernel