forked from M-Labs/artiq
ddb_template: edge counter keys correspond with according ttl keys
previously ttl_counter_0 and ttl_0 could be on completely different physical ttl output channels with this change, ttl_0_counter (note the changed key format) is always on the same channel as ttl_0 Signed-off-by: Leon Riesebos <leon.riesebos@duke.edu>
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@ -22,6 +22,8 @@ Highlights:
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* ``get()``, ``get_mu()``, ``get_att()``, and ``get_att_mu()`` functions added for AD9910 and AD9912
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* New hardware support:
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- HVAMP_8CH 8 channel HV amplifier for Fastino / Zotino
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* ``artiq_ddb_template`` generates edge-counter keys that start with the key of the corresponding
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TTL device (e.g. ``"ttl_0_counter"`` for the edge counter on TTL device``"ttl_0"``)
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Breaking changes:
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@ -82,7 +82,7 @@ class PeripheralManager:
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def gen(self, string, **kwargs):
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print(textwrap.dedent(string).format(**kwargs), file=self.output)
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def process_dio(self, rtio_offset, peripheral):
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def process_dio(self, rtio_offset, peripheral, num_channels=8):
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class_names = {
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"input": "TTLInOut",
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"output": "TTLOut"
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@ -92,7 +92,8 @@ class PeripheralManager:
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class_names[peripheral["bank_direction_high"]]
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]
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channel = count(0)
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for i in range(8):
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name = [self.get_name("ttl") for _ in range(num_channels)]
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for i in range(num_channels):
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self.gen("""
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device_db["{name}"] = {{
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"type": "local",
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@ -101,22 +102,22 @@ class PeripheralManager:
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"arguments": {{"channel": 0x{channel:06x}}},
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}}
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""",
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name=self.get_name("ttl"),
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name=name[i],
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class_name=classes[i // 4],
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channel=rtio_offset + next(channel))
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if peripheral.get("edge_counter", False):
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for i in range(8):
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for i in range(num_channels):
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class_name = classes[i // 4]
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if class_name == "TTLInOut":
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self.gen("""
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device_db["{name}"] = {{
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device_db["{name}_counter"] = {{
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"type": "local",
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"module": "artiq.coredevice.edge_counter",
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"class": "EdgeCounter",
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"arguments": {{"channel": 0x{channel:06x}}},
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}}
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""",
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name=self.get_name("ttl_counter"),
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name=name[i],
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channel=rtio_offset + next(channel))
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return next(channel)
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