forked from M-Labs/artiq
Merge pull request #1749 from airwoodix/phaser-frame-alignment-utils
Phaser: add helpers to align updates with RTIO timeline
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commit
e7a46ec767
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@ -18,6 +18,7 @@ Highlights:
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- Improved documentation
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- Expose the DAC coarse mixer and ``sif_sync``
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- Exposes upconverter calibration and enabling/disabling of upconverter LO & RF outputs.
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- Add helpers to align Phaser updates to the RTIO timeline (``get_next_frame_mu()``)
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* ``get()``, ``get_mu()``, ``get_att()``, and ``get_att_mu()`` functions added for AD9910 and AD9912
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* New hardware support:
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- HVAMP_8CH 8 channel HV amplifier for Fastino / Zotino
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@ -1,7 +1,7 @@
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from numpy import int32, int64
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from artiq.language.core import kernel, delay_mu, delay
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from artiq.coredevice.rtio import rtio_output, rtio_input_data
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from artiq.coredevice.rtio import rtio_output, rtio_input_data, rtio_input_timestamp
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from artiq.language.units import us, ns, ms, MHz
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from artiq.language.types import TInt32
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from artiq.coredevice.dac34h84 import DAC34H84
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@ -92,7 +92,8 @@ class Phaser:
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The latency/group delay from the RTIO events setting
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:class:`PhaserOscillator` or :class:`PhaserChannel` DUC parameters all the
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way to the DAC outputs is deterministic. This enables deterministic
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absolute phase with respect to other RTIO input and output events.
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absolute phase with respect to other RTIO input and output events
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(see `get_next_frame_mu()`).
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The four analog DAC outputs are passed through anti-aliasing filters.
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@ -160,6 +161,7 @@ class Phaser:
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# self.core.seconds_to_mu(10*8*4*ns) # unfortunately this returns 319
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assert self.core.ref_period == 1*ns
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self.t_frame = 10*8*4
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self.frame_tstamp = int64(0)
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self.clk_sel = clk_sel
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self.tune_fifo_offset = tune_fifo_offset
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self.sync_dly = sync_dly
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@ -188,7 +190,7 @@ class Phaser:
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gw_rev = self.read8(PHASER_ADDR_GW_REV)
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if debug:
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print(gw_rev)
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print("gw_rev:", gw_rev)
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self.core.break_realtime()
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delay(.1*ms) # slack
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@ -197,6 +199,11 @@ class Phaser:
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raise ValueError("large number of frame CRC errors")
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delay(.1*ms) # slack
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# determine the origin for frame-aligned timestamps
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self.measure_frame_timestamp()
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if self.frame_tstamp < 0:
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raise ValueError("frame timestamp measurement timed out")
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# reset
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self.set_cfg(dac_resetb=0, dac_sleep=1, dac_txena=0,
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trf0_ps=1, trf1_ps=1,
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@ -262,7 +269,7 @@ class Phaser:
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if self.tune_fifo_offset:
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fifo_offset = self.dac_tune_fifo_offset()
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if debug:
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print(fifo_offset)
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print("fifo_offset:", fifo_offset)
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self.core.break_realtime()
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# self.dac_write(0x20, 0x0000) # stop fifo sync
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@ -274,7 +281,7 @@ class Phaser:
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delay(.1*ms) # slack
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if alarms & ~0x0040: # ignore PLL alarms (see DS)
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if debug:
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print(alarms)
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print("alarms:", alarms)
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self.core.break_realtime()
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# ignore alarms
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else:
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@ -468,6 +475,27 @@ class Phaser:
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"""
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return self.read8(PHASER_ADDR_CRC_ERR)
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@kernel
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def measure_frame_timestamp(self):
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"""Measure the timestamp of an arbitrary frame and store it in `self.frame_tstamp`.
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To be used as reference for aligning updates to the FastLink frames.
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See `get_next_frame_mu()`.
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"""
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rtio_output(self.channel_base << 8, 0) # read any register
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self.frame_tstamp = rtio_input_timestamp(now_mu() + 4 * self.t_frame, self.channel_base)
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delay(100 * us)
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@kernel
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def get_next_frame_mu(self):
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"""Return the timestamp of the frame strictly after `now_mu()`.
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Register updates (DUC, DAC, TRF, etc.) scheduled at this timestamp and multiples
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of `self.t_frame` later will have deterministic latency to output.
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"""
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n = int64((now_mu() - self.frame_tstamp) / self.t_frame)
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return self.frame_tstamp + (n + 1) * self.t_frame
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@kernel
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def set_sync_dly(self, dly):
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"""Set SYNC delay.
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@ -860,7 +888,7 @@ class PhaserChannel:
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By default, the new NCO phase applies on completion of the SPI
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transfer. This also causes a staged NCO frequency to be applied.
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Different triggers for applying nco settings may be configured through
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Different triggers for applying NCO settings may be configured through
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the `syncsel_mixerxx` fields in the `dac` configuration dictionary (see
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`__init__()`).
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@ -878,7 +906,7 @@ class PhaserChannel:
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By default, the new NCO phase applies on completion of the SPI
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transfer. This also causes a staged NCO frequency to be applied.
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Different triggers for applying nco settings may be configured through
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Different triggers for applying NCO settings may be configured through
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the `syncsel_mixerxx` fields in the `dac` configuration dictionary (see
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`__init__()`).
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@ -1015,7 +1043,7 @@ class PhaserOscillator:
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"""Phaser IQ channel oscillator (NCO/DDS).
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.. note:: Latencies between oscillators within a channel and between
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oscillator paramters (amplitude and phase/frequency) are deterministic
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oscillator parameters (amplitude and phase/frequency) are deterministic
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(with respect to the 25 MS/s sample clock) but not matched.
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"""
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kernel_invariants = {"channel", "base_addr"}
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