artiqlib -> artiq.gateware

artiq/gateware/rtio/__init__.py

@@ -0,0 +1,2 @@
+from artiq.gateware.rtio import phy
+from artiq.gateware.rtio.core import RTIO

artiq/gateware/rtio/core.py

@@ -7,7 +7,7 @@ from migen.genlib.cdc import *
 from migen.genlib.fifo import AsyncFIFO
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
-from artiqlib.rtio.rbus import get_fine_ts_width
+from artiq.gateware.rtio.rbus import get_fine_ts_width
 
 
 class _GrayCodeTransfer(Module):

artiq/gateware/rtio/phy.py

@@ -1,7 +1,7 @@
 from migen.fhdl.std import *
 from migen.genlib.cdc import MultiReg
 
-from artiqlib.rtio.rbus import create_rbus
+from artiq.gateware.rtio.rbus import create_rbus
 
 
 class SimplePHY(Module):

soc/artiqlib/rtio/__init__.py

@@ -1,2 +0,0 @@
-from artiqlib.rtio import phy
-from artiqlib.rtio.core import RTIO

soc/targets/artiq_kc705.py

@@ -6,7 +6,7 @@ from mibuild.generic_platform import *
 from misoclib.cpu.peripherals import gpio
 from targets.kc705 import BaseSoC
 
-from artiqlib import rtio, ad9858
+from artiq.gateware import rtio, ad9858
 
 
 _tester_io = [

soc/targets/artiq_ppro.py

@@ -6,7 +6,7 @@ from mibuild.generic_platform import *
 from misoclib.cpu.peripherals import gpio
 from targets.ppro import BaseSoC
 
-from artiqlib import rtio, ad9858
+from artiq.gateware import rtio, ad9858
 
 
 _tester_io = [