From 28bce9ee40b1534ca304e88068f63a0402dd20f7 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Sun, 8 Mar 2015 11:00:24 +0100 Subject: [PATCH] artiqlib -> artiq.gateware --- artiq/gateware/__init__.py | 0 {soc/artiqlib => artiq/gateware}/ad9858.py | 0 artiq/gateware/rtio/__init__.py | 2 ++ {soc/artiqlib => artiq/gateware}/rtio/core.py | 2 +- {soc/artiqlib => artiq/gateware}/rtio/phy.py | 2 +- {soc/artiqlib => artiq/gateware}/rtio/rbus.py | 0 soc/artiqlib/rtio/__init__.py | 2 -- soc/targets/artiq_kc705.py | 2 +- soc/targets/artiq_ppro.py | 2 +- 9 files changed, 6 insertions(+), 6 deletions(-) create mode 100644 artiq/gateware/__init__.py rename {soc/artiqlib => artiq/gateware}/ad9858.py (100%) create mode 100644 artiq/gateware/rtio/__init__.py rename {soc/artiqlib => artiq/gateware}/rtio/core.py (99%) rename {soc/artiqlib => artiq/gateware}/rtio/phy.py (95%) rename {soc/artiqlib => artiq/gateware}/rtio/rbus.py (100%) delete mode 100644 soc/artiqlib/rtio/__init__.py diff --git a/artiq/gateware/__init__.py b/artiq/gateware/__init__.py new file mode 100644 index 000000000..e69de29bb diff --git a/soc/artiqlib/ad9858.py b/artiq/gateware/ad9858.py similarity index 100% rename from soc/artiqlib/ad9858.py rename to artiq/gateware/ad9858.py diff --git a/artiq/gateware/rtio/__init__.py b/artiq/gateware/rtio/__init__.py new file mode 100644 index 000000000..f170e8354 --- /dev/null +++ b/artiq/gateware/rtio/__init__.py @@ -0,0 +1,2 @@ +from artiq.gateware.rtio import phy +from artiq.gateware.rtio.core import RTIO diff --git a/soc/artiqlib/rtio/core.py b/artiq/gateware/rtio/core.py similarity index 99% rename from soc/artiqlib/rtio/core.py rename to artiq/gateware/rtio/core.py index 01504047b..b6303d253 100644 --- a/soc/artiqlib/rtio/core.py +++ b/artiq/gateware/rtio/core.py @@ -7,7 +7,7 @@ from migen.genlib.cdc import * from migen.genlib.fifo import AsyncFIFO from migen.genlib.resetsync import AsyncResetSynchronizer -from artiqlib.rtio.rbus import get_fine_ts_width +from artiq.gateware.rtio.rbus import get_fine_ts_width class _GrayCodeTransfer(Module): diff --git a/soc/artiqlib/rtio/phy.py b/artiq/gateware/rtio/phy.py similarity index 95% rename from soc/artiqlib/rtio/phy.py rename to artiq/gateware/rtio/phy.py index 5ce082982..d1526adb6 100644 --- a/soc/artiqlib/rtio/phy.py +++ b/artiq/gateware/rtio/phy.py @@ -1,7 +1,7 @@ from migen.fhdl.std import * from migen.genlib.cdc import MultiReg -from artiqlib.rtio.rbus import create_rbus +from artiq.gateware.rtio.rbus import create_rbus class SimplePHY(Module): diff --git a/soc/artiqlib/rtio/rbus.py b/artiq/gateware/rtio/rbus.py similarity index 100% rename from soc/artiqlib/rtio/rbus.py rename to artiq/gateware/rtio/rbus.py diff --git a/soc/artiqlib/rtio/__init__.py b/soc/artiqlib/rtio/__init__.py deleted file mode 100644 index 9c20b7171..000000000 --- a/soc/artiqlib/rtio/__init__.py +++ /dev/null @@ -1,2 +0,0 @@ -from artiqlib.rtio import phy -from artiqlib.rtio.core import RTIO diff --git a/soc/targets/artiq_kc705.py b/soc/targets/artiq_kc705.py index f70eabaab..f3077a91f 100644 --- a/soc/targets/artiq_kc705.py +++ b/soc/targets/artiq_kc705.py @@ -6,7 +6,7 @@ from mibuild.generic_platform import * from misoclib.cpu.peripherals import gpio from targets.kc705 import BaseSoC -from artiqlib import rtio, ad9858 +from artiq.gateware import rtio, ad9858 _tester_io = [ diff --git a/soc/targets/artiq_ppro.py b/soc/targets/artiq_ppro.py index 23f73bc3d..e641b7e3f 100644 --- a/soc/targets/artiq_ppro.py +++ b/soc/targets/artiq_ppro.py @@ -6,7 +6,7 @@ from mibuild.generic_platform import * from misoclib.cpu.peripherals import gpio from targets.ppro import BaseSoC -from artiqlib import rtio, ad9858 +from artiq.gateware import rtio, ad9858 _tester_io = [