forked from M-Labs/artiq
drtio: add rt_controller_repeater
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@ -10,7 +10,8 @@ from artiq.gateware.rtio.sed.core import *
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from artiq.gateware.rtio.input_collector import *
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from artiq.gateware.drtio import (link_layer, aux_controller,
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rt_packet_satellite, rt_errors_satellite,
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rt_packet_master, rt_controller_master)
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rt_packet_master, rt_controller_master,
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rt_controller_repeater)
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from artiq.gateware.drtio.rx_synchronizer import GenericRXSynchronizer
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@ -188,6 +189,7 @@ class DRTIORepeater(Module):
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self.submodules.link_stats = link_layer.LinkLayerStats(self.link_layer, "rtio_rx")
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self.submodules.rt_packet = rt_packet_repeater.RTPacketRepeater(tsc, self.link_layer)
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self.submodules.rt_controller = rt_controller_repeater.RTController(self.rt_packet)
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self.submodules.aux_controller = aux_controller.AuxController(
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self.link_layer)
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@ -195,6 +197,7 @@ class DRTIORepeater(Module):
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def get_csrs(self):
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return (self.link_layer.get_csrs() +
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self.link_stats.get_csrs() +
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self.rt_controller.get_csrs() +
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self.aux_controller.get_csrs())
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@property
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@ -0,0 +1,42 @@
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from migen import *
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from misoc.interconnect.csr import *
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from artiq.gateware.rtio.cdc import BlindTransfer
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class RTController(Module, AutoCSR):
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def __init__(self, rt_packet):
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self.set_time = CSR()
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self.protocol_error = CSR(4)
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set_time_stb = Signal()
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set_time_ack = Signal()
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self.submodules += CrossDomainRequest("rtio",
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set_time_stb, set_time_ack, None,
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rt_packet.set_time_stb, rt_packet.set_time_ack, None)
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self.sync += [
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If(set_time_ack, set_time_stb.eq(0)),
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If(self.set_time.re, set_time_stb.eq(1))
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]
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self.comb += self.set_time.w.eq(set_time_stb)
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errors = [
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(rt_packet.err_unknown_packet_type, "rtio_rx"),
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(rt_packet.err_packet_truncated, "rtio_rx"),
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(rt_packet.err_command_missed, "rtio"),
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(rt_packet.err_buffer_space_timeout, "rtio")
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]
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for n, (err_i, err_cd) in enumerate(errors):
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xfer = BlindTransfer(err_cd, "sys")
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self.submodules += xfer
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self.comb += xfer.i.eq(err_i)
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err_pending = Signal()
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self.sync += [
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If(self.protocol_error.re & self.protocol_error.r[n], err_pending.eq(0)),
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If(xfer.o, err_pending.eq(1))
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]
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self.comb += self.protocol_error.w[n].eq(err_pending)
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@ -18,8 +18,8 @@ class RTPacketRepeater(Module):
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self.err_packet_truncated = Signal()
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# in rtio domain
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self.command_missed = Signal()
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self.buffer_space_timeout = Signal()
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self.err_command_missed = Signal()
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self.err_buffer_space_timeout = Signal()
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# set_time interface, in rtio domain
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self.set_time_stb = Signal()
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@ -103,7 +103,7 @@ class RTPacketRepeater(Module):
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# Missed commands
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cri_ready = Signal()
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self.sync.rtio += self.command_missed.eq(~cri_ready & (self.cri.cmd != cri.commands["nop"]))
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self.sync.rtio += self.err_command_missed.eq(~cri_ready & (self.cri.cmd != cri.commands["nop"]))
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# TX FSM
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tx_fsm = ClockDomainsRenamer("rtio")(FSM(reset_state="IDLE"))
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@ -158,7 +158,7 @@ class RTPacketRepeater(Module):
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tx_fsm.act("WAIT_BUFFER_SPACE",
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timeout_counter.wait.eq(1),
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If(timeout_counter.done,
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self.buffer_space_timeout.eq(1),
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self.err_buffer_space_timeout.eq(1),
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NextState("IDLE")
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).Else(
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If(buffer_space_not,
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