srenblad
/
artiq
forked from M-Labs/artiq
1
0
Fork 0
Code Pull Requests Activity

drtio: add external TSC to repeater

This commit is contained in:
Sebastien Bourdeauducq 2018-09-05 15:55:20 +08:00
parent 5f20d79408
commit 839f748a1d
3 changed files with 15 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
artiq/gateware/drtio/core.py
View File

@ -181,13 +181,13 @@ class DRTIOMaster(Module):
class DRTIORepeater(Module):
def __init__(self, chanif):
def __init__(self, tsc, chanif):
self.submodules.link_layer = link_layer.LinkLayer(
chanif.encoder, chanif.decoders)
self.comb += self.link_layer.rx_ready.eq(chanif.rx_ready)
self.submodules.link_stats = link_layer.LinkLayerStats(self.link_layer, "rtio_rx")
self.submodules.rt_packet = rt_packet_repeater.RTPacketRepeater(self.link_layer)
self.submodules.rt_packet = rt_packet_repeater.RTPacketRepeater(tsc, self.link_layer)
self.submodules.aux_controller = aux_controller.AuxController(
self.link_layer)

5
artiq/gateware/drtio/rt_packet_repeater.py
View File

@ -9,7 +9,7 @@ from artiq.gateware.drtio.rt_serializer import *
class RTPacketRepeater(Module):
def __init__(self, link_layer):
def __init__(self, tsc, link_layer):
# CRI target interface in rtio domain
self.cri = cri.Interface()
@ -24,7 +24,6 @@ class RTPacketRepeater(Module):
# set_time interface, in rtio domain
self.set_time_stb = Signal()
self.set_time_ack = Signal()
self.tsc_value = Signal(64)
# # #
@ -44,7 +43,7 @@ class RTPacketRepeater(Module):
# TSC sync
tsc_value = Signal(64)
tsc_value_load = Signal()
self.sync.rtio += If(tsc_value_load, tsc_value.eq(self.tsc_value))
self.sync.rtio += If(tsc_value_load, tsc_value.eq(tsc.coarse_ts))
# Write buffer and extra data count
wb_timestamp = Signal(64)

19
artiq/gateware/test/drtio/test_rt_packet_repeater.py
View File

@ -11,20 +11,23 @@ from artiq.gateware.drtio.rt_packet_repeater import RTPacketRepeater
def create_dut(nwords):
pt = PacketInterface("s2m", nwords*8)
pr = PacketInterface("m2s", nwords*8)
ts = Signal(64)
dut = ClockDomainsRenamer({"rtio": "sys", "rtio_rx": "sys"})(
RTPacketRepeater(SimpleNamespace(
rx_rt_frame=pt.frame, rx_rt_data=pt.data,
tx_rt_frame=pr.frame, tx_rt_data=pr.data)))
return pt, pr, dut
RTPacketRepeater(
SimpleNamespace(coarse_ts=ts),
SimpleNamespace(
rx_rt_frame=pt.frame, rx_rt_data=pt.data,
tx_rt_frame=pr.frame, tx_rt_data=pr.data)))
return pt, pr, ts, dut
class TestRepeater(unittest.TestCase):
def test_set_time(self):
nwords = 2
pt, pr, dut = create_dut(nwords)
pt, pr, ts, dut = create_dut(nwords)
def send():
yield dut.tsc_value.eq(0x12345678)
yield ts.eq(0x12345678)
yield dut.set_time_stb.eq(1)
while not (yield dut.set_time_ack):
yield
@ -55,7 +58,7 @@ class TestRepeater(unittest.TestCase):
]
for nwords in range(1, 8):
pt, pr, dut = create_dut(nwords)
pt, pr, ts, dut = create_dut(nwords)
def send():
for channel, timestamp, address, data in test_writes:
@ -89,7 +92,7 @@ class TestRepeater(unittest.TestCase):
def test_buffer_space(self):
for nwords in range(1, 8):
pt, pr, dut = create_dut(nwords)
pt, pr, ts, dut = create_dut(nwords)
def send_requests():
for i in range(10):