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pipistrello: add notes to nist_qc1 about dds_clock 

* remove xtrig from the target as it is not usually connected (used for
  dds_clock) and ignore PMT2/BTN2 as C:15 is used for dds_clock.
* this also aligns the ttl channel numbers with kc705/nist_qc1 (two pmt
  inputs followed by 16 ttl outputs followed by leds)
This commit is contained in:
Robert Jördens 2015-06-28 20:33:50 -06:00
parent 5442ae312f
commit 23eee94458
2 changed files with 20 additions and 6 deletions
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16
artiq/gateware/nist_qc1.py
View File

@ -4,10 +4,22 @@ from mibuild.generic_platform import *
papilio_adapter_io = [ papilio_adapter_io = [
("ext_led", 0, Pins("B:7"), IOStandard("LVTTL")), ("ext_led", 0, Pins("B:7"), IOStandard("LVTTL")),
# to feed the 125 MHz clock (preferrably from DDS SYNC_CLK)
# to the FPGA, use the xtrig pair.
#
# on papiliopro-adapter, xtrig (C:12) is connected to a GCLK
#
# on pipistrello, C:15 is the only GCLK in proximity, used as a button
# input, BTN2/PMT2 in papiliopro-adapter
# either improve the DDS box to feed 125MHz into the PMT2 pair, or:
#
# * disconnect C:15 from its periphery on the adapter board
# * bridge C:15 to the xtrig output of the transciever
# * optionally, disconnect C:12 from its periphery
("xtrig", 0, Pins("C:12"), IOStandard("LVTTL")),
("pmt", 0, Pins("C:13"), IOStandard("LVTTL")), ("pmt", 0, Pins("C:13"), IOStandard("LVTTL")),
("pmt", 1, Pins("C:14"), IOStandard("LVTTL")), ("pmt", 1, Pins("C:14"), IOStandard("LVTTL")),
("xtrig", 0, Pins("C:12"), IOStandard("LVTTL")), ("pmt", 2, Pins("C:15"), IOStandard("LVTTL")), # rarely equipped
("dds_clock", 0, Pins("C:15"), IOStandard("LVTTL")), # PMT2
("ttl", 0, Pins("C:11"), IOStandard("LVTTL")), ("ttl", 0, Pins("C:11"), IOStandard("LVTTL")),
("ttl", 1, Pins("C:10"), IOStandard("LVTTL")), ("ttl", 1, Pins("C:10"), IOStandard("LVTTL")),

10
soc/targets/artiq_pipistrello.py
View File

@ -34,7 +34,7 @@ class _RTIOCRG(Module, AutoCSR):
i_FREEZEDCM=0, i_FREEZEDCM=0,
i_RST=ResetSignal()) i_RST=ResetSignal())
rtio_external_clk = platform.request("dds_clock") rtio_external_clk = platform.request("pmt", 2)
platform.add_period_constraint(rtio_external_clk, 8.0) platform.add_period_constraint(rtio_external_clk, 8.0)
self.specials += Instance("BUFGMUX", self.specials += Instance("BUFGMUX",
i_I0=rtio_internal_clk, i_I0=rtio_internal_clk,
@ -95,11 +95,13 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd
for i in range(2): for i in range(2):
phy = ttl_simple.Inout(platform.request("pmt", i)) phy = ttl_simple.Inout(platform.request("pmt", i))
self.submodules += phy self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512)) rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512,
ofifo_depth=4))
phy = ttl_simple.Inout(platform.request("xtrig", 0)) phy = ttl_simple.Inout(platform.request("xtrig"))
self.submodules += phy self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4)) rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4,
ofifo_depth=4))
for i in range(16): for i in range(16):
phy = ttl_simple.Output(platform.request("ttl", i)) phy = ttl_simple.Output(platform.request("ttl", i))