From 23eee9445833d90e8bef1757914e8f0b5e1ba9ca Mon Sep 17 00:00:00 2001 From: Robert Jordens Date: Sun, 28 Jun 2015 20:33:50 -0600 Subject: [PATCH] pipistrello: add notes to nist_qc1 about dds_clock * remove xtrig from the target as it is not usually connected (used for dds_clock) and ignore PMT2/BTN2 as C:15 is used for dds_clock. * this also aligns the ttl channel numbers with kc705/nist_qc1 (two pmt inputs followed by 16 ttl outputs followed by leds) --- artiq/gateware/nist_qc1.py | 16 ++++++++++++++-- soc/targets/artiq_pipistrello.py | 10 ++++++---- 2 files changed, 20 insertions(+), 6 deletions(-) diff --git a/artiq/gateware/nist_qc1.py b/artiq/gateware/nist_qc1.py index a2d68e44f..f75f52371 100644 --- a/artiq/gateware/nist_qc1.py +++ b/artiq/gateware/nist_qc1.py @@ -4,10 +4,22 @@ from mibuild.generic_platform import * papilio_adapter_io = [ ("ext_led", 0, Pins("B:7"), IOStandard("LVTTL")), + # to feed the 125 MHz clock (preferrably from DDS SYNC_CLK) + # to the FPGA, use the xtrig pair. + # + # on papiliopro-adapter, xtrig (C:12) is connected to a GCLK + # + # on pipistrello, C:15 is the only GCLK in proximity, used as a button + # input, BTN2/PMT2 in papiliopro-adapter + # either improve the DDS box to feed 125MHz into the PMT2 pair, or: + # + # * disconnect C:15 from its periphery on the adapter board + # * bridge C:15 to the xtrig output of the transciever + # * optionally, disconnect C:12 from its periphery + ("xtrig", 0, Pins("C:12"), IOStandard("LVTTL")), ("pmt", 0, Pins("C:13"), IOStandard("LVTTL")), ("pmt", 1, Pins("C:14"), IOStandard("LVTTL")), - ("xtrig", 0, Pins("C:12"), IOStandard("LVTTL")), - ("dds_clock", 0, Pins("C:15"), IOStandard("LVTTL")), # PMT2 + ("pmt", 2, Pins("C:15"), IOStandard("LVTTL")), # rarely equipped ("ttl", 0, Pins("C:11"), IOStandard("LVTTL")), ("ttl", 1, Pins("C:10"), IOStandard("LVTTL")), diff --git a/soc/targets/artiq_pipistrello.py b/soc/targets/artiq_pipistrello.py index 6f5e6f632..65b6e4cea 100644 --- a/soc/targets/artiq_pipistrello.py +++ b/soc/targets/artiq_pipistrello.py @@ -34,7 +34,7 @@ class _RTIOCRG(Module, AutoCSR): i_FREEZEDCM=0, i_RST=ResetSignal()) - rtio_external_clk = platform.request("dds_clock") + rtio_external_clk = platform.request("pmt", 2) platform.add_period_constraint(rtio_external_clk, 8.0) self.specials += Instance("BUFGMUX", i_I0=rtio_internal_clk, @@ -95,11 +95,13 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd for i in range(2): phy = ttl_simple.Inout(platform.request("pmt", i)) self.submodules += phy - rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512)) + rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512, + ofifo_depth=4)) - phy = ttl_simple.Inout(platform.request("xtrig", 0)) + phy = ttl_simple.Inout(platform.request("xtrig")) self.submodules += phy - rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4)) + rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4, + ofifo_depth=4)) for i in range(16): phy = ttl_simple.Output(platform.request("ttl", i))