forked from M-Labs/artiq
Commit missing parts of 9366a29
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@ -42,7 +42,7 @@ def cache_get(key: TStr) -> TList(TInt32):
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raise NotImplementedError("syscall not simulated")
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@syscall
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def cache_put(key: TStr, value: TList(TInt32)):
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def cache_put(key: TStr, value: TList(TInt32)) -> TNone:
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raise NotImplementedError("syscall not simulated")
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class Core:
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@ -940,9 +940,12 @@ static int process_kmsg(struct msg_base *umsg)
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case MESSAGE_TYPE_FINISHED:
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out_packet_empty(REMOTEMSG_TYPE_KERNEL_FINISHED);
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for(struct cache_row *iter = cache; iter; iter = iter->next)
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iter->borrowed = 0;
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kloader_stop();
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user_kernel_state = USER_KERNEL_LOADED;
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mailbox_acknowledge();
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break;
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case MESSAGE_TYPE_EXCEPTION: {
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@ -1031,9 +1034,11 @@ static int process_kmsg(struct msg_base *umsg)
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}
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if(!row) {
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struct cache_row *row = calloc(1, sizeof(struct cache_row));
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row = calloc(1, sizeof(struct cache_row));
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row->key = calloc(strlen(request->key) + 1, 1);
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strcpy(row->key, request->key);
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row->next = cache;
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cache = row;
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}
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if(!row->borrowed) {
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@ -0,0 +1,44 @@
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from artiq.language import *
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from artiq.coredevice.exceptions import *
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from artiq.test.hardware_testbench import ExperimentCase
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class _Cache(EnvExperiment):
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def build(self):
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self.setattr_device("core")
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self.print = lambda x: print(x)
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@kernel
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def get(self, key):
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return self.core.get_cache(key)
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@kernel
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def put(self, key, value):
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self.core.put_cache(key, value)
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@kernel
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def get_put(self, key, value):
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self.get(key)
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self.put(key, value)
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class CacheTest(ExperimentCase):
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def test_get_empty(self):
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exp = self.create(_Cache)
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self.assertEqual(exp.get("x1"), [])
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def test_put_get(self):
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exp = self.create(_Cache)
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exp.put("x2", [1, 2, 3])
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self.assertEqual(exp.get("x2"), [1, 2, 3])
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def test_replace(self):
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exp = self.create(_Cache)
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exp.put("x3", [1, 2, 3])
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exp.put("x3", [1, 2, 3, 4, 5])
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self.assertEqual(exp.get("x3"), [1, 2, 3, 4, 5])
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def test_borrow(self):
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exp = self.create(_Cache)
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exp.put("x4", [1, 2, 3])
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with self.assertRaises(CacheError):
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exp.get_put("x4", [])
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