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adf5356: add delay to sync() 

Signed-off-by: Oi Chee Cheung <dc@m-labs.hk>
This commit is contained in:
occheung 2021-07-08 10:03:13 +08:00
parent b10d1bdd37
commit 2204fd2b22
2 changed files with 4 additions and 0 deletions
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2
RELEASE_NOTES.rst
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@ -27,6 +27,8 @@ Breaking changes:
* ``Phaser.init()`` now disables all Kasli-oscillators. This avoids full power RF output being * ``Phaser.init()`` now disables all Kasli-oscillators. This avoids full power RF output being
generated for some configurations. generated for some configurations.
* Phaser: fixed coarse mixer frequency configuration * Phaser: fixed coarse mixer frequency configuration
* Mirny: Added extra delays in ``ADF5356.sync()``. This avoids the need of an extra delay before
calling `ADF5356.init()`.
ARTIQ-6 ARTIQ-6

2
artiq/coredevice/adf5356.py
View File

@ -236,6 +236,7 @@ class ADF5356:
Write all registers to the device. Attempts to lock the PLL. Write all registers to the device. Attempts to lock the PLL.
""" """
f_pfd = self.f_pfd() f_pfd = self.f_pfd()
delay(200 * us) # Slack
if f_pfd <= 75.0 * MHz: if f_pfd <= 75.0 * MHz:
for i in range(13, 0, -1): for i in range(13, 0, -1):
@ -249,6 +250,7 @@ class ADF5356:
n, frac1, (frac2_msb, frac2_lsb), (mod2_msb, mod2_lsb) = calculate_pll( n, frac1, (frac2_msb, frac2_lsb), (mod2_msb, mod2_lsb) = calculate_pll(
self.f_vco(), f_pfd >> 1 self.f_vco(), f_pfd >> 1
) )
delay(200 * us) # Slack
self.write( self.write(
13 13