forked from M-Labs/artiq
test: change base address in DMA simulation testbench
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245e186347
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200c499114
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@ -23,7 +23,7 @@ def encode_record(channel, timestamp, address, data):
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r += encode_n(channel, 3, 3)
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r += encode_n(timestamp, 8, 8)
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r += encode_n(address, 2, 2)
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r += encode_n(data, 4, 64)
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r += encode_n(data, 1, 64)
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return encode_n(len(r)+1, 1, 1) + r
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@ -37,24 +37,45 @@ def pack(x, size):
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n |= x[j]
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except IndexError:
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pass
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# print("{:0128x}".format(n))
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r.append(n)
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return r
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test_writes = [
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def encode_sequence(writes, ws):
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sequence = [b for write in writes for b in encode_record(*write)]
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sequence.append(0)
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return pack(sequence, ws)
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test_writes1 = [
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(0x01, 0x23, 0x12, 0x33),
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(0x901, 0x902, 0x911, 0xeeeeeeeeeeeeeefffffffffffffffffffffffffffffff28888177772736646717738388488),
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(0x81, 0x288, 0x88, 0x8888)
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]
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test_writes2 = [
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(0x10, 0x10000, 0x20, 0x77),
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(0x11, 0x10001, 0x22, 0x7777),
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(0x12, 0x10002, 0x30, 0x777777),
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(0x13, 0x10003, 0x40, 0x77777788),
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(0x14, 0x10004, 0x50, 0x7777778899),
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]
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prng = random.Random(0)
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class TB(Module):
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def __init__(self, ws):
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sequence = [b for write in test_writes for b in encode_record(*write)]
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sequence.append(0)
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# print(sequence)
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sequence = pack(sequence, ws)
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sequence1 = encode_sequence(test_writes1, ws)
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sequence2 = encode_sequence(test_writes2, ws)
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offset = 512//ws
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assert len(sequence1) < offset
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sequence = (
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sequence1 +
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[prng.randrange(2**(ws*8)) for _ in range(offset-len(sequence1))] +
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sequence2)
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bus = wishbone.Interface(ws*8)
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self.submodules.memory = wishbone.SRAM(
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@ -64,16 +85,19 @@ class TB(Module):
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class TestDMA(unittest.TestCase):
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def test_dma_noerror(self):
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prng = random.Random(0)
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ws = 64
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tb = TB(ws)
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def do_dma():
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for i in range(2):
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yield from tb.dut.enable.write(1)
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def do_dma(address):
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yield from tb.dut.dma.base_address.write(address)
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yield from tb.dut.enable.write(1)
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yield
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while ((yield from tb.dut.enable.read())):
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yield
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while ((yield from tb.dut.enable.read())):
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yield
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def do_writes():
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yield from do_dma(0)
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yield from do_dma(512)
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received = []
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@passive
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@ -98,5 +122,5 @@ class TestDMA(unittest.TestCase):
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self.fail("unexpected RTIO command")
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yield
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run_simulation(tb, [do_dma(), rtio_sim()])
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self.assertEqual(received, test_writes*2)
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run_simulation(tb, [do_writes(), rtio_sim()])
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self.assertEqual(received, test_writes1 + test_writes2)
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