forked from M-Labs/artiq
drtio: fix gtx_7series comma alignment
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a4ba34bb2c
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1d027ffa95
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@ -185,7 +185,7 @@ class GTX_1000BASE_BX10(Module):
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self.decoders[1].input.eq(rxdata[10:])
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self.decoders[1].input.eq(rxdata[10:])
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]
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]
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clock_aligner = BruteforceClockAligner(0b0011111000, self.rtio_clk_freq)
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clock_aligner = BruteforceClockAligner(0b0001111100, self.rtio_clk_freq)
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self.submodules += clock_aligner
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self.submodules += clock_aligner
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self.comb += [
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self.comb += [
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clock_aligner.rxdata.eq(rxdata),
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clock_aligner.rxdata.eq(rxdata),
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@ -118,7 +118,7 @@ class GTXInit(Module):
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# Changes the phase of the transceiver RX clock to align the comma to
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# Changes the phase of the transceiver RX clock to align the comma to
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# the MSBs of RXDATA, fixing the latency.
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# the LSBs of RXDATA, fixing the latency.
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#
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#
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# This is implemented by repeatedly resetting the transceiver until it
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# This is implemented by repeatedly resetting the transceiver until it
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# gives out the correct phase. Each reset gives a random phase.
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# gives out the correct phase. Each reset gives a random phase.
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@ -130,6 +130,9 @@ class GTXInit(Module):
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# * RXSLIDE_MODE=PMA cannot be used with the RX buffer bypassed.
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# * RXSLIDE_MODE=PMA cannot be used with the RX buffer bypassed.
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# Those design flaws make RXSLIDE_MODE=PMA yet another broken and useless
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# Those design flaws make RXSLIDE_MODE=PMA yet another broken and useless
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# transceiver "feature".
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# transceiver "feature".
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#
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# Warning: Xilinx transceivers are LSB first, and comma needs to be flipped
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# compared to the usual 8b10b binary representation.
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class BruteforceClockAligner(Module):
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class BruteforceClockAligner(Module):
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def __init__(self, comma, rtio_clk_freq, check_period=6e-3, ready_time=50e-3):
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def __init__(self, comma, rtio_clk_freq, check_period=6e-3, ready_time=50e-3):
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self.rxdata = Signal(20)
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self.rxdata = Signal(20)
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@ -156,6 +159,7 @@ class BruteforceClockAligner(Module):
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comma_n = ~comma & 0b1111111111
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comma_n = ~comma & 0b1111111111
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comma_seen_rxclk = Signal()
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comma_seen_rxclk = Signal()
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comma_seen = Signal()
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comma_seen = Signal()
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comma_seen_rxclk.attr.add("no_retiming")
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self.specials += MultiReg(comma_seen_rxclk, comma_seen)
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self.specials += MultiReg(comma_seen_rxclk, comma_seen)
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comma_seen_reset = PulseSynchronizer("rtio", "rtio_rx")
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comma_seen_reset = PulseSynchronizer("rtio", "rtio_rx")
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self.submodules += comma_seen_reset
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self.submodules += comma_seen_reset
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