From 1d027ffa95904f14de4d580037f0d647b69578a4 Mon Sep 17 00:00:00 2001
From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Thu, 3 Nov 2016 20:13:50 +0800
Subject: [PATCH] drtio: fix gtx_7series comma alignment

---
 artiq/gateware/drtio/transceiver/gtx_7series.py      | 2 +-
 artiq/gateware/drtio/transceiver/gtx_7series_init.py | 6 +++++-
 2 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/artiq/gateware/drtio/transceiver/gtx_7series.py b/artiq/gateware/drtio/transceiver/gtx_7series.py
index b768ae470..4d2f66e13 100644
--- a/artiq/gateware/drtio/transceiver/gtx_7series.py
+++ b/artiq/gateware/drtio/transceiver/gtx_7series.py
@@ -185,7 +185,7 @@ class GTX_1000BASE_BX10(Module):
             self.decoders[1].input.eq(rxdata[10:])
         ]
 
-        clock_aligner = BruteforceClockAligner(0b0011111000, self.rtio_clk_freq)
+        clock_aligner = BruteforceClockAligner(0b0001111100, self.rtio_clk_freq)
         self.submodules += clock_aligner
         self.comb += [
             clock_aligner.rxdata.eq(rxdata),
diff --git a/artiq/gateware/drtio/transceiver/gtx_7series_init.py b/artiq/gateware/drtio/transceiver/gtx_7series_init.py
index c46e3eef0..cf502ec24 100644
--- a/artiq/gateware/drtio/transceiver/gtx_7series_init.py
+++ b/artiq/gateware/drtio/transceiver/gtx_7series_init.py
@@ -118,7 +118,7 @@ class GTXInit(Module):
 
 
 # Changes the phase of the transceiver RX clock to align the comma to
-# the MSBs of RXDATA, fixing the latency.
+# the LSBs of RXDATA, fixing the latency.
 #
 # This is implemented by repeatedly resetting the transceiver until it
 # gives out the correct phase. Each reset gives a random phase.
@@ -130,6 +130,9 @@ class GTXInit(Module):
 #  * RXSLIDE_MODE=PMA cannot be used with the RX buffer bypassed.
 # Those design flaws make RXSLIDE_MODE=PMA yet another broken and useless
 # transceiver "feature".
+#
+# Warning: Xilinx transceivers are LSB first, and comma needs to be flipped
+# compared to the usual 8b10b binary representation.
 class BruteforceClockAligner(Module):
     def __init__(self, comma, rtio_clk_freq, check_period=6e-3, ready_time=50e-3):
         self.rxdata = Signal(20)
@@ -156,6 +159,7 @@ class BruteforceClockAligner(Module):
         comma_n = ~comma & 0b1111111111
         comma_seen_rxclk = Signal()
         comma_seen = Signal()
+        comma_seen_rxclk.attr.add("no_retiming")
         self.specials += MultiReg(comma_seen_rxclk, comma_seen)
         comma_seen_reset = PulseSynchronizer("rtio", "rtio_rx")
         self.submodules += comma_seen_reset