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sayma: tune SYSREF phases

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Sebastien Bourdeauducq 2018-07-12 11:30:57 +08:00
parent 773240bef4
commit 1c191a62bf
2 changed files with 4 additions and 4 deletions
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4
artiq/firmware/runtime/main.rs
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@ -57,9 +57,9 @@ mod moninj;
mod analyzer; mod analyzer;
#[cfg(has_ad9154)] #[cfg(has_ad9154)]
const SYSREF_PHASE_FPGA: u16 = 35; const SYSREF_PHASE_FPGA: u16 = 41;
#[cfg(has_ad9154)] #[cfg(has_ad9154)]
const SYSREF_PHASE_DAC: u16 = 64; const SYSREF_PHASE_DAC: u16 = 94;
fn startup() { fn startup() {
irq::set_mask(0); irq::set_mask(0);

4
artiq/firmware/satman/main.rs
View File

@ -250,9 +250,9 @@ fn drtio_link_rx_up() -> bool {
const SIPHASER_PHASE: u16 = 32; const SIPHASER_PHASE: u16 = 32;
#[cfg(has_ad9154)] #[cfg(has_ad9154)]
const SYSREF_PHASE_FPGA: u16 = 53; const SYSREF_PHASE_FPGA: u16 = 54;
#[cfg(has_ad9154)] #[cfg(has_ad9154)]
const SYSREF_PHASE_DAC: u16 = 64; const SYSREF_PHASE_DAC: u16 = 61;
#[no_mangle] #[no_mangle]
pub extern fn main() -> i32 { pub extern fn main() -> i32 {