From 1c191a62bf7c3ae582d15712a29ac7dfa3590705 Mon Sep 17 00:00:00 2001
From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Thu, 12 Jul 2018 11:30:57 +0800
Subject: [PATCH] sayma: tune SYSREF phases

---
 artiq/firmware/runtime/main.rs | 4 ++--
 artiq/firmware/satman/main.rs  | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/artiq/firmware/runtime/main.rs b/artiq/firmware/runtime/main.rs
index 2f119515a..cc67b64c4 100644
--- a/artiq/firmware/runtime/main.rs
+++ b/artiq/firmware/runtime/main.rs
@@ -57,9 +57,9 @@ mod moninj;
 mod analyzer;
 
 #[cfg(has_ad9154)]
-const SYSREF_PHASE_FPGA: u16 = 35;
+const SYSREF_PHASE_FPGA: u16 = 41;
 #[cfg(has_ad9154)]
-const SYSREF_PHASE_DAC: u16 = 64;
+const SYSREF_PHASE_DAC: u16 = 94;
 
 fn startup() {
     irq::set_mask(0);
diff --git a/artiq/firmware/satman/main.rs b/artiq/firmware/satman/main.rs
index faac96946..b8a256fcd 100644
--- a/artiq/firmware/satman/main.rs
+++ b/artiq/firmware/satman/main.rs
@@ -250,9 +250,9 @@ fn drtio_link_rx_up() -> bool {
 
 const SIPHASER_PHASE: u16 = 32;
 #[cfg(has_ad9154)]
-const SYSREF_PHASE_FPGA: u16 = 53;
+const SYSREF_PHASE_FPGA: u16 = 54;
 #[cfg(has_ad9154)]
-const SYSREF_PHASE_DAC: u16 = 64;
+const SYSREF_PHASE_DAC: u16 = 61;
 
 #[no_mangle]
 pub extern fn main() -> i32 {