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gateware/rt2wb: only input when active

This commit is contained in:
Robert Jördens 2016-02-29 14:56:29 +01:00
parent 6903a1d88a
commit 1b08e65fa1
1 changed files with 1 additions and 1 deletions
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artiq/gateware/rtio/phy/wishbone.py
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@ -39,6 +39,6 @@ class RT2WB(Module):
wb.cyc.eq(active), wb.cyc.eq(active),
wb.stb.eq(active), wb.stb.eq(active),
self.rtlink.i.stb.eq(wb.ack & ~wb.we), self.rtlink.i.stb.eq(active & wb.ack & ~wb.we),
self.rtlink.i.data.eq(wb.dat_r) self.rtlink.i.data.eq(wb.dat_r)
] ]