From 1b08e65fa1ffc616e2b74c0f875b6193ce7a01a3 Mon Sep 17 00:00:00 2001 From: Robert Jordens Date: Mon, 29 Feb 2016 14:56:29 +0100 Subject: [PATCH] gateware/rt2wb: only input when active --- artiq/gateware/rtio/phy/wishbone.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/artiq/gateware/rtio/phy/wishbone.py b/artiq/gateware/rtio/phy/wishbone.py index 1b58525f6..429e2c8ce 100644 --- a/artiq/gateware/rtio/phy/wishbone.py +++ b/artiq/gateware/rtio/phy/wishbone.py @@ -39,6 +39,6 @@ class RT2WB(Module): wb.cyc.eq(active), wb.stb.eq(active), - self.rtlink.i.stb.eq(wb.ack & ~wb.we), + self.rtlink.i.stb.eq(active & wb.ack & ~wb.we), self.rtlink.i.data.eq(wb.dat_r) ]