From 18d18b668569104a4735ee06b1d253171c7f1119 Mon Sep 17 00:00:00 2001 From: Robert Jordens Date: Mon, 10 Oct 2016 16:13:50 +0200 Subject: [PATCH] phaser: add sync ttl input for monitoring --- artiq/examples/phaser/device_db.pyon | 14 ++++++++++---- artiq/gateware/targets/kc705.py | 19 +++++++++++++------ doc/manual/core_device.rst | 4 +++- 3 files changed, 26 insertions(+), 11 deletions(-) diff --git a/artiq/examples/phaser/device_db.pyon b/artiq/examples/phaser/device_db.pyon index f1b441921..c9bfe06f5 100644 --- a/artiq/examples/phaser/device_db.pyon +++ b/artiq/examples/phaser/device_db.pyon @@ -44,28 +44,34 @@ "class": "TTLInOut", "arguments": {"channel": 2} }, + "sync": { + "type": "local", + "module": "artiq.coredevice.ttl", + "class": "TTLInOut", + "arguments": {"channel": 3} + }, "sawg0": { "type": "local", "module": "artiq.coredevice.sawg", "class": "SAWG", - "arguments": {"channel_base": 3, "parallelism": 4} + "arguments": {"channel_base": 4, "parallelism": 4} }, "sawg1": { "type": "local", "module": "artiq.coredevice.sawg", "class": "SAWG", - "arguments": {"channel_base": 6, "parallelism": 4} + "arguments": {"channel_base": 7, "parallelism": 4} }, "sawg2": { "type": "local", "module": "artiq.coredevice.sawg", "class": "SAWG", - "arguments": {"channel_base": 9, "parallelism": 4} + "arguments": {"channel_base": 10, "parallelism": 4} }, "sawg3": { "type": "local", "module": "artiq.coredevice.sawg", "class": "SAWG", - "arguments": {"channel_base": 12, "parallelism": 4} + "arguments": {"channel_base": 13, "parallelism": 4} } } diff --git a/artiq/gateware/targets/kc705.py b/artiq/gateware/targets/kc705.py index 257dc381f..67bdc2ab8 100755 --- a/artiq/gateware/targets/kc705.py +++ b/artiq/gateware/targets/kc705.py @@ -149,8 +149,10 @@ class _NIST_Ions(MiniSoC, AMPSoC): self.register_kernel_cpu_csrdevice("i2c") self.config["I2C_BUS_COUNT"] = 1 - def add_rtio(self, rtio_channels, crg=_RTIOCRG): - self.submodules.rtio_crg = crg(self.platform, self.crg.cd_sys.clk) + def add_rtio(self, rtio_channels, rtio_crg=None): + if rtio_crg is None: + rtio_crg = _RTIOCRG(self.platform, self.crg.cd_sys.clk) + self.submodules.rtio_crg = rtio_crg self.csr_devices.append("rtio_crg") self.submodules.rtio = rtio.RTIO(rtio_channels) self.register_kernel_cpu_csrdevice("rtio") @@ -454,6 +456,7 @@ class AD9154(Module, AutoCSR): jesd_sync = Signal() self.specials += DifferentialInput( sync_pads.p, sync_pads.n, jesd_sync) + self.jesd_sync = jesd_sync ps = JESD204BPhysicalSettings(l=4, m=4, n=16, np=16) ts = JESD204BTransportSettings(f=2, s=1, k=16, cs=1) @@ -510,6 +513,12 @@ class Phaser(_NIST_Ions): rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=32, ofifo_depth=2)) + jesd_sync = Signal() + phy = ttl_simple.Input(jesd_sync) + self.submodules += phy + rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=32, + ofifo_depth=2)) + self.config["RTIO_REGULAR_TTL_COUNT"] = len(rtio_channels) self.config["RTIO_FIRST_SAWG_CHANNEL"] = len(rtio_channels) @@ -522,11 +531,8 @@ class Phaser(_NIST_Ions): self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels) rtio_channels.append(rtio.LogChannel()) - self.add_rtio(rtio_channels, _PhaserCRG) + self.add_rtio(rtio_channels, _PhaserCRG(platform, self.crg.cd_sys.clk)) - # jesd_sysref = Signal() - # self.specials += DifferentialInput( - # sysref_pads.p, sysref_pads.n, jesd_sysref) to_rtio = ClockDomainsRenamer({"sys": "rtio"}) self.submodules.ad9154 = to_rtio(AD9154(platform, self.rtio_crg)) self.register_kernel_cpu_csrdevice("ad9154") @@ -537,6 +543,7 @@ class Phaser(_NIST_Ions): "converter{}".format(i)) # while at 5 GBps, take every second sample... FIXME self.comb += conv.eq(Cat(ch.o[::2])) + self.comb += jesd_sync.eq(self.ad9154.jesd_sync) def main(): diff --git a/doc/manual/core_device.rst b/doc/manual/core_device.rst index 7f48d719a..389e11fa4 100644 --- a/doc/manual/core_device.rst +++ b/doc/manual/core_device.rst @@ -170,8 +170,10 @@ The Phaser adapter is an AD9154-FMC-EBZ, a 4 channel 2.4 GHz DAC on an FMC HPC c +--------------+------------+--------------+ | 2 | SYSREF | Input | +--------------+------------+--------------+ +| 3 | SYNC | Input | ++--------------+------------+--------------+ -The SAWG channels start with RTIO channel number 3, each occupying 3 channels. +The SAWG channels start with RTIO channel number 4, each occupying 3 channels. The board has one non-RTIO SPI bus that is accessible through :mod:`artiq.coredevice.ad9154`.